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    Process options of forming silicided metal gates for advanced CMOS devices
    7.
    发明授权
    Process options of forming silicided metal gates for advanced CMOS devices 有权
    为先进的CMOS器件形成硅化金属栅的工艺选择

    公开(公告)号：US07326610B2

    公开(公告)日：2008-02-05

    申请号：US11271032

    申请日：2005-11-10

    申请人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

    发明人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

    摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

    摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

    Process options of forming silicided metal gates for advanced CMOS devices
    8.
    发明授权
    Process options of forming silicided metal gates for advanced CMOS devices 失效
    为先进的CMOS器件形成硅化金属栅的工艺选择

    公开(公告)号：US07029966B2

    公开(公告)日：2006-04-18

    申请号：US10605261

    申请日：2003-09-18

    申请人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

    发明人： Ricky S. Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Evgeni P. Gousev ,  Victor Ku ,  An Steegen

    IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

    摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

    摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

    MEMS varactors
    10.
    发明授权
    MEMS varactors 有权
    MEMS变容二极管

    公开(公告)号：US08363380B2

    公开(公告)日：2013-01-29

    申请号：US12473882

    申请日：2009-05-28

    申请人： Je-Hsiung Lan ,  Evgeni P. Gousev ,  Wenyue Zhang ,  Manish Kothari ,  Sang-June Park

    发明人： Je-Hsiung Lan ,  Evgeni P. Gousev ,  Wenyue Zhang ,  Manish Kothari ,  Sang-June Park

    IPC分类号： H01G7/00 ,  H01G7/06

    CPC分类号： H01G7/00 ,  H01G5/16 ,  H01P1/127 ,  Y10T29/435

    摘要： MEMS varactors capable of handling large signals and/or achieving a high capacitance tuning range are described. In an exemplary design, a MEMS varactor includes (i) a first bottom plate electrically coupled to a first terminal receiving an input signal, (ii) a second bottom plate electrically coupled to a second terminal receiving a DC voltage, and (iii) a top plate formed over the first and second bottom plates and electrically coupled to a third terminal. The DC voltage causes the top plate to mechanically move and vary the capacitance observed by the input signal. In another exemplary design, a MEMS varactor includes first, second and third plates formed on over one another and electrically coupled to first, second and third terminals, respectively. First and second DC voltages may be applied to the first and third terminals, respectively. An input signal may be passed between the first and second terminals.

    摘要翻译： 描述能够处理大信号和/或实现高电容调谐范围的MEMS变容二极管。 在示例性设计中，MEMS变容二极管包括（i）电耦合到接收输入信号的第一端子的第一底板，（ii）电耦合到接收DC电压的第二端子的第二底板，以及（iii） 顶板形成在第一和第二底板上并电耦合到第三端子。 直流电压使顶板机械地移动并改变由输入信号观察到的电容。 在另一示例性设计中，MEMS变容二极管包括彼此形成并分别电耦合到第一，第二和第三端子的第一，第二和第三板。 第一和第二直流电压可以分别施加到第一和第三端子。 输入信号可以在第一和第二端子之间通过。