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公开(公告)号：US4417159A
公开(公告)日：1983-11-22
申请号：US293830
申请日：1981-08-18
IPC分类号： H03F1/00 , H03K5/02 , H03K17/04 , H03K17/06 , H03K17/12 , H03K17/66 , H03K19/013 , H03K19/018 , H03K5/00
CPC分类号： H03K19/013 , H03K19/01806 , H03K5/02
摘要： A driver circuit for a capacitively loaded line employs the charge storage capacitance of a diode for raising the base of a driver transistor above the circuit power supply voltage level so as to pull up the line to within a transistor base-emitter voltage drop of the power supply voltage level. The driver is easily fabricated in integrated circuit form, as no capacitors, either on or off chip, are required.The driver circuit includes a driver transistor, the collector of which is connected to the power supply and the emitter of which is connected to the line. A switching transistor has an input voltage applied between its base and emitter. A diode is connected between the switching and driver transistors, the anode being connected to the base of the driver transistor, and the cathode being connected to the collector of the switching transistor.In response to a first input signal, the switching transistor turns on, forward biasing the diode and building up a voltage thereon as a result of the diode's charge storage capacitance. In response to a second input signal, the switching transistor turns off, raising the anode to the power supply voltage, and raising the cathode (and the base of the driver transistor connected thereto) to a voltage higher than the power supply voltage. The emitter of the driver transistor (and the line connected thereto) is thus pulled up to a value nominally approaching the power supply voltage, despite the base-emitter voltage drop of the driver transistor.
摘要翻译： 用于电容负载线路的驱动器电路采用用于将驱动晶体管的基极升高到电路电源电压电平以上的二极管的电荷存储电容，以便将线上拉到功率的晶体管基极 - 发射极电压降内 电源电压电平。 驱动器易于以集成电路形式制造，因为不需要电源或芯片上的电容器。 驱动器电路包括驱动晶体管，其集电极连接到电源，其发射极连接到线路。 开关晶体管具有施加在其基极和发射极之间的输入电压。 二极管连接在开关晶体管和驱动晶体管之间，阳极连接到驱动晶体管的基极，阴极连接到开关晶体管的集电极。 响应于第一输入信号，开关晶体管导通，由于二极管的电荷存储电容，正向偏置二极管并在其上建立电压。 响应于第二输入信号，开关晶体管截止，将阳极升高到电源电压，并将阴极（以及连接到其的驱动晶体管的基极）升高到高于电源电压的电压。 因此，尽管驱动晶体管的基极 - 发射极电压降，驱动晶体管（及其连接的线）的发射极被上拉到标称接近电源电压的值。
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2.发明授权Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay 失效功率控制装置，用于消除电路与电路延迟差异并提供所需的电路延迟
公开(公告)号：US4346343A
公开(公告)日：1982-08-24
申请号：US150762
申请日：1980-05-16
IPC分类号： H03K19/00 , G05F1/46 , G06F1/04 , G06F1/10 , H03K3/03 , H03K5/00 , H03K19/0175 , H03K19/086 , H03L7/089 , H03L7/099
CPC分类号： H03L7/0805 , G05F1/466 , H03K3/0315 , H03K3/0322 , H03L7/0995 , H03L7/089
摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock).
摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将参考信号与对电源变化敏感的片上产生信号进行比较来实现，这些信号对于批次处理变化，温度等是很敏感的。比较产生用于改变功率的误差信号（ 电流或电压）提供给片上电路。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。
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公开(公告)号：US4508981A
公开(公告)日：1985-04-02
申请号：US392982
申请日：1982-06-28
IPC分类号： H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06 , H03K17/16 , H03K3/013 , H03K19/003
CPC分类号： H03K17/16
摘要： Compensation circuit means for inclusion in an off-chip driver circuit is provided to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. The compensation circuit means, which is coupled across the output transistor circuit of the off-chip driver, may comprise one or more serially connected diodes. The diode (or diodes) may be formed by the base collector junction of a bipolar transistor.
摘要翻译： 提供了用于包含在片外驱动电路中的补偿电路，以减少多芯片模块半导体结构中的自感应开关噪声。 模块部分互连芯片，芯片分别具有电源和电源引线。 耦合在片外驱动器的输出晶体管电路两端的补偿电路装置可以包括一个或多个串联连接的二极管。 二极管（或二极管）可以由双极晶体管的基极集电极结形成。
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4.发明授权AC Measurement means for use with power control means for eliminating circuit to circuit delay differences 失效AC测量装置，用于消除电路与电路延迟差异的功率控制装置
公开(公告)号：US4383216A
公开(公告)日：1983-05-10
申请号：US229417
申请日：1981-01-29
IPC分类号： H01L21/822 , G05F1/46 , G06F1/08 , H01L27/00 , H01L27/04 , H03K5/00 , H03K19/00 , H03K19/0175
CPC分类号： G05F1/466
摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock). At least certain of the chips include an AC measurement circuit for comparing the periodicity of said reference signal with the periodicity of said on generated chip signal and cooperating with the delay regulator thereof to provide one of three discrete electrical manifestations.
摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将周期性参考信号与对电源变化，批次处理变化，温度等敏感的周期性片上产生信号进行比较来实现。比较创建一个误差信号，用于改变 提供给片上电路的功率（电流或电压）。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。 至少某些芯片包括AC测量电路，用于将所述参考信号的周期性与所述上述生成的芯片信号的周期进行比较，并与其延迟调节器协作以提供三种离散电气表现之一。
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公开(公告)号：US4829198A
公开(公告)日：1989-05-09
申请号：US37306
申请日：1987-04-10
IPC分类号： H03K19/003 , H03K19/00 , H03K19/007
CPC分类号： H03K19/0075
摘要： A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.
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6.发明授权Integrated dynamic power dissipation control system for very large scale integrated (VLSI) chips 失效用于大规模集成（VLSI）芯片的集成动态功耗控制系统
公开(公告)号：US5485127A
公开(公告)日：1996-01-16
申请号：US418849
申请日：1995-04-07
摘要： Chip logic, a frequency multiplication and/or division, a temperature sensing circuit, and a power management circuit, are integrated on a very large scale integrated (VLSI) circuit chip. The temperature sensing circuit directly measures the chip temperature, producing a temperature output signal. The power management circuit, which is connected to the temperature sensing circuit and to the chip logic, responds to the temperature output signal and to a functional state of the chip logic to generate a control signal to the PLL. The PLL responds to the control signal to either stop the clock signal or modify the operating frequency of the clock signal, depending upon the state of the control signal.
摘要翻译： 芯片逻辑，倍频和/或除法，温度感测电路和电源管理电路集成在大规模集成（VLSI）电路芯片上。 温度检测电路直接测量芯片温度，产生温度输出信号。 连接到温度检测电路和芯片逻辑的电源管理电路响应于温度输出信号和芯片逻辑的功能状态，以产生到PLL的控制信号。 根据控制信号的状态，PLL响应控制信号以停止时钟信号或修改时钟信号的工作频率。
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公开(公告)号：US06550013B1
公开(公告)日：2003-04-15
申请号：US09388952
申请日：1999-09-02
IPC分类号： G06F108
CPC分类号： G06F1/08
摘要： A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.
摘要翻译： 实现了存储器时钟发生器装置和方法。 从处理器时钟产生存储器时钟“开环”。 处理器时钟被选通并通过移位寄存器传播。 从移位寄存器中抽出的一组输出与多个控制信号一起被解码，并且以“或”逻辑进行解码，以生成可以以存储器时钟速率的预定倍数运行的时钟输出。 时钟输出可以具有存储器时钟周期与处理器时钟周期的多个比率中的一个。 控制信号选择比例。 时钟发生器可以异步启动，并且另外，发生器向具有与时钟发生器的开始具有预定时间关系的边沿的处理器输出信号。
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公开(公告)号：US07301385B2
公开(公告)日：2007-11-27
申请号：US11233423
申请日：2005-09-22
申请人： Chiaki Takano , Stephen D. Weitzel
发明人： Chiaki Takano , Stephen D. Weitzel
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.
摘要翻译： 公开了一种装置，其包括提供具有第一频率的第一信号的信号发生器; 时钟树，用于将所述第一信号传播到所述装置的至少一个时钟网格; 以及最终缓冲器，用于接收第一信号，提供具有第二频率的第二信号，使第二信号与第一信号同步，并将同步的第二信号传播到装置的至少一个其它时钟网格。
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公开(公告)号：US07262636B2
公开(公告)日：2007-08-28
申请号：US11154765
申请日：2005-06-16
IPC分类号： H03K19/0175
CPC分类号： H03K19/00323
摘要： Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.
摘要翻译： 公开了具有基本相等的传播延迟同时提供不同驱动强度的电路的系统和方法。 这些系统和方法可以允许具有任意强度全驱动强度电路的一些比率的驱动强度的电路。 此外，这些电路可以具有与基线驱动电路基本相同的输入电容和反馈电流。 这种电路的输入可以耦合到三个节点，其中一个是耦合到待驱动逻辑的反相器，其中第二个是虚拟逻辑，第三个是反相器，其输出是悬空的 。
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