-
1.发明授权AC Measurement means for use with power control means for eliminating circuit to circuit delay differences 失效AC测量装置，用于消除电路与电路延迟差异的功率控制装置
公开(公告)号：US4383216A
公开(公告)日：1983-05-10
申请号：US229417
申请日：1981-01-29
IPC分类号： H01L21/822 , G05F1/46 , G06F1/08 , H01L27/00 , H01L27/04 , H03K5/00 , H03K19/00 , H03K19/0175
CPC分类号： G05F1/466
摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock). At least certain of the chips include an AC measurement circuit for comparing the periodicity of said reference signal with the periodicity of said on generated chip signal and cooperating with the delay regulator thereof to provide one of three discrete electrical manifestations.
摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将周期性参考信号与对电源变化，批次处理变化，温度等敏感的周期性片上产生信号进行比较来实现。比较创建一个误差信号，用于改变 提供给片上电路的功率（电流或电压）。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。 至少某些芯片包括AC测量电路，用于将所述参考信号的周期性与所述上述生成的芯片信号的周期进行比较，并与其延迟调节器协作以提供三种离散电气表现之一。
-
公开(公告)号：US06738248B1
公开(公告)日：2004-05-18
申请号：US10281811
申请日：2002-10-28
IPC分类号： H02H322
CPC分类号： H01L27/0255
摘要： An over-voltage protected integrated circuit is provided, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.
摘要翻译： 提供了一种过电压保护的集成电路，其包括放电节点，输入 - 输出焊盘，耦合到输入 - 输出焊盘的信号迹线以及一对背对背二极管，其耦合 在第一信号迹线和放电节点之间。
-
3.发明授权Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency 失效用于测试一对串行数据收发器以一个频率传输串行数据并以另一频率接收串行数据的能力的装置和方法公开(公告)号：US06208621B1
公开(公告)日：2001-03-27
申请号：US08991906
申请日：1997-12-16
IPC分类号： H04L1226
摘要： An apparatus and method are presented for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency. A serial communication device of the present invention includes a first and second serial data transceivers and a multiplexer formed upon a monolithic semiconductor substrate. Each serial data transceiver includes a receiver and a transmitter which transmits serial data in response to a clock signal. The second serial data transceiver is coupled to receive a reference clock signal. The multiplexer facilitates testing, and is coupled to the first serial data transceiver. The multiplexer receives the reference clock signal, a test clock signal, and a test signal, and provides either the reference clock signal or the test clock signal to the first transceiver dependent upon the test signal. The reference and test clock signals have different frequencies. The multiplexer provides the reference clock signal to the first transceiver when the test signal is deasserted, and provides the test clock signal to the first transceiver when the test signal is asserted. During testing, the output of the transmitter of one transceiver is coupled to the input of the receiver of the other transceiver, and the test signal is asserted. Each receiver produces parallel output test data. A match between the two sets of parallel output test data and the parallel input test data demonstrates the abilities of both transceivers to transmit and receive serial data at different frequencies.
摘要翻译： 提出了一种用于测试一对串行数据收发器以一个频率传输串行数据并以另一频率接收串行数据的能力的装置和方法。 本发明的串行通信设备包括第一和第二串行数据收发器以及形成在单片半导体衬底上的多路复用器。 每个串行数据收发器包括一个接收器和一个响应时钟信号发送串行数据的发送器。 第二串行数据收发器被耦合以接收参考时钟信号。 多路复用器便于测试，并且耦合到第一串行数据收发器。 多路复用器接收参考时钟信号，测试时钟信号和测试信号，并根据测试信号将参考时钟信号或测试时钟信号提供给第一收发器。 参考和测试时钟信号具有不同的频率。 当测试信号被断言时，多路复用器将参考时钟信号提供给第一收发器，并且当测试信号被断言时，将测试时钟信号提供给第一收发器。 在测试期间，一个收发器的发射机的输出耦合到另一个收发器的接收机的输入，并且测试信号被断言。 每个接收机产生并行输出测试数据。 两组并行输出测试数据和并行输入测试数据之间的匹配表明两个收发器在不同频率下发送和接收串行数据的能力。
-
4.发明授权Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method 失效串行数据收发器包括便于仅访问串行数据端口的功能测试的元件，以及相关的测试方法公开(公告)号：US06341142B2
公开(公告)日：2002-01-22
申请号：US08991715
申请日：1997-12-16
IPC分类号： H04L516
CPC分类号： H04B3/46
摘要： A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver. A test method involves asserting the test signal, providing serial input test data to a serial data input port, receiving serial output test data from a serial data output port, and comparing the serial output test data to the serial input test data. A match between the serial output test data and the serial input test data verifies proper operation of the serial data transceiver.
摘要翻译： 提出了一种串行数据收发器，其包括仅使用收发器的串行数据传输终端进行测试的元件。 串行数据收发器包括发射机和接收机。 发送器接收并行数据，将并行数据转换为串行数据流，并发送串行数据流。 接收器接收串行数据流，将串行数据流转换为并行数据，并提供并行数据。 在测试期间，由接收机产生的并行数据被路由到发射机输入。 在一个实施例中，发射机包括用于将并行输入数据路由到发射机的第一路由器，并且接收机包括用于路由由接收机产生的并行输出数据的第二路由器。 第一路由器耦合到第二路由器，两个路由器都接收测试信号。 当测试信号被断言时，第二路由器将由接收机产生的并行输出数据路由到第一路由器，并且第一路由器将由接收机产生的并行输出数据路由到发射机。 结果，接收到的串行数据由收发器重传。 测试方法包括断言测试信号，向串行数据输入端口提供串行输入测试数据，从串行数据输出端口接收串行输出测试数据，以及将串行输出测试数据与串行输入测试数据进行比较。 串行输出测试数据和串行输入测试数据之间的匹配验证串行数据收发器的正确操作。
-
5.发明授权High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network 失效高速串行线收发器集成到高速缓存控制器中，以支持松散耦合网络中的一致存储器事务公开(公告)号：US06330591B1
公开(公告)日：2001-12-11
申请号：US09036897
申请日：1998-03-09
IPC分类号： G06F1338
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0817
摘要： One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent. Each transmit unit comprises a receiver operably coupled between an input port and an output port, and a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. Also included are a transmitter which receives parallel data and transmits a serial data stream. The parallel data are received concurrently with the serialized data being received. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream.
摘要翻译： 一个或多个改进的发射单元与控制器紧密集成到增强型集群高速缓存中。 通过将所有计算机连接到所有其他计算机的高速，低延迟和高带宽串行线路将松散耦合的计算机网络中的所有计算机发送所有缓存更新，从而支持松散耦合的计算机网络中的相干内存事务。 集群高速缓存控制器可以包括本地高速缓存控制器和/或作为本地总线控制器。 本地总线控制器可操作以将集群高速缓存耦合到I / O子系统。 本地高速缓冲存储器优选地为整个计算机高速缓存数据和/或指令或其位置，使得本地计算机缓存可通过发送单元对整个计算机集群可用。 每个传输单元是一个全双工收发器，包括发射机和接收机功能。 每个传送单元可以同时发送和接收数据，因为其发射机和接收机功能的操作是独立的。 每个发射单元包括可操作地耦合在输入端口和输出端口之间的接收器，以及连接到从串行化数据恢复时钟信号并使来自恢复时钟的反序列化数据同步的定时发生器。 还包括接收并行数据并发送串行数据流的发送器。 与正在接收的序列化数据同时接收并行数据。 解串器耦合以将序列化数据转换为反序列化数据。 串行器被耦合以将并行数据转换成串行数据流。
-
公开(公告)号：US08913688B1
公开(公告)日：2014-12-16
申请号：US13460527
申请日：2012-04-30
申请人： Michael O. Jenkins
发明人： Michael O. Jenkins
CPC分类号： H04L7/0025 , H03F1/3241 , H03F1/3282 , H03L7/081 , H03L7/091 , H04L7/0087
摘要： An embodiment of an apparatus for nonlinearity compensation is disclosed. For an embodiment, a pre-distorter is coupled to receive a first signal. The pre-distorter is configured to convert first values of the first signal into second values for a second signal. The pre-distorter includes a converter for converting the first values to the second values. A phase interpolator is coupled to receive the second signal. The second values are associated with nonlinearity of the phase interpolator. The phase interpolator is configured to provide an interpolated output from the second signal. The second signal is adjusted for the nonlinearity of the phase interpolator by use of the second values.
摘要翻译： 公开了一种非线性补偿装置的实施例。 对于一个实施例，预失真器被耦合以接收第一信号。 预失真器被配置为将第一信号的第一值转换为第二信号的第二值。 预失真器包括用于将第一值转换为第二值的转换器。 耦合相位内插器以接收第二信号。 第二个值与相位内插器的非线性相关。 相位插值器被配置为从第二信号提供内插输出。 通过使用第二值来调整第二信号对于相位插值器的非线性。
-
公开(公告)号：US06490325B1
公开(公告)日：2002-12-03
申请号：US09164245
申请日：1998-09-30
IPC分类号： H04B300
CPC分类号： H03H7/38
摘要： A data transmission circuit for transmitting a data stream includes a voltage supply terminal, a resistively terminated, controlled-impedance transmission line and an inductor coupled between the voltage supply terminal and the controlled-impedance transmission line.
摘要翻译： 用于发送数据流的数据传输电路包括电压供给端子，电阻端接的受控阻抗传输线和耦合在电压提供端子和受控阻抗传输线之间的电感器。
-
8.发明授权System for sending data from-and-to a computer monitor using a high speed serial line 失效使用高速串行线路将数据发送到计算机显示器的系统
公开(公告)号：US6061747A
公开(公告)日：2000-05-09
申请号：US951530
申请日：1997-10-16
CPC分类号： G09G5/006 , G09G2370/04 , G09G5/008
摘要： An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact. The computer system may include the remote transceiver for transmitting a return serial data stream, a transmitter operably coupled between the feedback input port and the remote serial output port, and a timing generator coupled to recover a clock signal from the serial data stream and to synchronize the deserialized data. The base transceiver may also include a serial input port for receiving the return serial data stream, a receiver operably coupled to the serial input port, and a return high speed serial connection between the remote serial output port and the base serial input port. The return serial data stream is received concurrent with the serial data stream being received.
摘要翻译： 改进的收发器对，紧密集成到计算机系统中。 收发器对包括基地收发器和远程收发器，它们之间具有高速串行连接。 基地收发器具有基本发射机，具有用于接受并行编码数据的并行输入端口和用于发送串行编码数据流的串行输出端口。 远程收发器具有接收器，其具有用于接收串行编码数据流的串行输入端口和用于在解码之后将反序列化数据传送到音频和视频控制单元的音频/视频输出端口。 高速串行连接将基本串行输出端口连接到远程串行输入端口。 远程接收器还包括适于接收从传感器转发的反馈数据的反馈输入端口。 传感器可能响应可触及，光学或声音输入或物理接触。 计算机系统可以包括用于发送返回串行数据流的远程收发器，可操作地耦合在反馈输入端口和远程串行输出端口之间的发送器以及耦合以从串行数据流恢复时钟信号并同步的定时发生器 反序列化数据。 基本收发器还可以包括用于接收返回串行数据流的串行输入端口，可操作地耦合到串行输入端口的接收器以及远程串行输出端口和基本串行输入端口之间的返回高速串行连接。 与正在接收的串行数据流同时接收返回串行数据流。
-
公开(公告)号：US5570356A
公开(公告)日：1996-10-29
申请号：US486541
申请日：1995-06-07
CPC分类号： H04Q11/04
摘要： A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.
摘要翻译： 数据通信系统包括：将高速并行数据字分割为若干个并行数据字节的相位分离电路，分相电路的每个相位的字节多路复用器，用于转换每个字节的编码和串行化电路， 一个8位字节到适合于串行传输的编码形式，例如通过使用Widmer等人 8位/ 10位代码，将多个串行传输链路之一的每个编码字节传送到数据被反序列化和解码的接收设备，以恢复原始字节，然后由字节同步电路同步。 字节同步电路然后被耦合到字同步电路，其中原始高带宽数据字被恢复并在接收设备内的内部高速并行总线上传输。
-
公开(公告)号：US08823133B2
公开(公告)日：2014-09-02
申请号：US13075059
申请日：2011-03-29
申请人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
发明人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
IPC分类号： H01L27/08 , H01L25/18 , H01L23/60 , H01L23/64 , H01L23/498 , H01L25/065
CPC分类号： H01L23/645 , H01L23/49822 , H01L23/60 , H01L23/642 , H01L25/0655 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01019 , H01L2924/15192 , H01L2924/15311 , H01L2224/0401
摘要： An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.
摘要翻译： 公开了一种多芯片模块的实施例。 对于多芯片模块的该实施例，包括半导体管芯和插入件。 插入器具有导电层，电介质层和衬底。 内部互连结构将半导体管芯耦合到插入器。 外部互连结构用于将插入器耦合到外部设备。 第一电感器包括插入器的一个或多个导电层的至少一部分。 第一电感器的第一端耦合到内部互连结构的内部互连结构。 第一电感器的第二端耦合到外部互连结构的外部互连结构。
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.024 秒)