公开(公告)号：US4346343A

公开(公告)日：1982-08-24

申请号：US150762

申请日：1980-05-16

申请人： Erich Berndlmaier ,  Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Erich Berndlmaier ,  Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H03K19/00 ,  G05F1/46 ,  G06F1/04 ,  G06F1/10 ,  H03K3/03 ,  H03K5/00 ,  H03K19/0175 ,  H03K19/086 ,  H03L7/089 ,  H03L7/099

CPC分类号： H03L7/0805 ,  G05F1/466 ,  H03K3/0315 ,  H03K3/0322 ,  H03L7/0995 ,  H03L7/089

摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock).

摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将参考信号与对电源变化敏感的片上产生信号进行比较来实现，这些信号对于批次处理变化，温度等是很敏感的。比较产生用于改变功率的误差信号（ 电流或电压）提供给片上电路。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。

公开(公告)号：US4417159A

公开(公告)日：1983-11-22

申请号：US293830

申请日：1981-08-18

申请人： Jack A. Dorler ,  Joseph M. Mosley ,  Richard O. Seeger ,  Stephen D. Weitzel

发明人： Jack A. Dorler ,  Joseph M. Mosley ,  Richard O. Seeger ,  Stephen D. Weitzel

IPC分类号： H03F1/00 ,  H03K5/02 ,  H03K17/04 ,  H03K17/06 ,  H03K17/12 ,  H03K17/66 ,  H03K19/013 ,  H03K19/018 ,  H03K5/00

CPC分类号： H03K19/013 ,  H03K19/01806 ,  H03K5/02

摘要： A driver circuit for a capacitively loaded line employs the charge storage capacitance of a diode for raising the base of a driver transistor above the circuit power supply voltage level so as to pull up the line to within a transistor base-emitter voltage drop of the power supply voltage level. The driver is easily fabricated in integrated circuit form, as no capacitors, either on or off chip, are required.The driver circuit includes a driver transistor, the collector of which is connected to the power supply and the emitter of which is connected to the line. A switching transistor has an input voltage applied between its base and emitter. A diode is connected between the switching and driver transistors, the anode being connected to the base of the driver transistor, and the cathode being connected to the collector of the switching transistor.In response to a first input signal, the switching transistor turns on, forward biasing the diode and building up a voltage thereon as a result of the diode's charge storage capacitance. In response to a second input signal, the switching transistor turns off, raising the anode to the power supply voltage, and raising the cathode (and the base of the driver transistor connected thereto) to a voltage higher than the power supply voltage. The emitter of the driver transistor (and the line connected thereto) is thus pulled up to a value nominally approaching the power supply voltage, despite the base-emitter voltage drop of the driver transistor.

摘要翻译： 用于电容负载线路的驱动器电路采用用于将驱动晶体管的基极升高到电路电源电压电平以上的二极管的电荷存储电容，以便将线上拉到功率的晶体管基极 - 发射极电压降内 电源电压电平。 驱动器易于以集成电路形式制造，因为不需要电源或芯片上的电容器。 驱动器电路包括驱动晶体管，其集电极连接到电源，其发射极连接到线路。 开关晶体管具有施加在其基极和发射极之间的输入电压。 二极管连接在开关晶体管和驱动晶体管之间，阳极连接到驱动晶体管的基极，阴极连接到开关晶体管的集电极。 响应于第一输入信号，开关晶体管导通，由于二极管的电荷存储电容，正向偏置二极管并在其上建立电压。 响应于第二输入信号，开关晶体管截止，将阳极升高到电源电压，并将阴极（以及连接到其的驱动晶体管的基极）升高到高于电​​源电压的电压。 因此，尽管驱动晶体管的基极 - 发射极电压降，驱动晶体管（及其连接的线）的发射极被上拉到标称接近电源电压的值。

公开(公告)号：US4508981A

公开(公告)日：1985-04-02

申请号：US392982

申请日：1982-06-28

申请人： Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K17/16 ,  H03K3/013 ,  H03K19/003

CPC分类号： H03K17/16

摘要： Compensation circuit means for inclusion in an off-chip driver circuit is provided to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. The compensation circuit means, which is coupled across the output transistor circuit of the off-chip driver, may comprise one or more serially connected diodes. The diode (or diodes) may be formed by the base collector junction of a bipolar transistor.

摘要翻译： 提供了用于包含在片外驱动电路中的补偿电路，以减少多芯片模块半导体结构中的自感应开关噪声。 模块部分互连芯片，芯片分别具有电源和电源引线。 耦合在片外驱动器的输出晶体管电路两端的补偿电路装置可以包括一个或多个串联连接的二极管。 二极管（或二极管）可以由双极晶体管的基极集电极结形成。

公开(公告)号：US4383216A

公开(公告)日：1983-05-10

申请号：US229417

申请日：1981-01-29

申请人： Jack A. Dorler ,  Michael O. Jenkins ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Jack A. Dorler ,  Michael O. Jenkins ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H01L21/822 ,  G05F1/46 ,  G06F1/08 ,  H01L27/00 ,  H01L27/04 ,  H03K5/00 ,  H03K19/00 ,  H03K19/0175

CPC分类号： G05F1/466

摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock). At least certain of the chips include an AC measurement circuit for comparing the periodicity of said reference signal with the periodicity of said on generated chip signal and cooperating with the delay regulator thereof to provide one of three discrete electrical manifestations.

摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将周期性参考信号与对电源变化，批次处理变化，温度等敏感的周期性片上产生信号进行比较来实现。比较创建一个误差信号，用于改变 提供给片上电路的功率（电流或电压）。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。 至少某些芯片包括AC测量电路，用于将所述参考信号的周期性与所述上述生成的芯片信号的周期进行比较，并与其延迟调节器协作以提供三种离散电气表现之一。

公开(公告)号：US4535531A

公开(公告)日：1985-08-20

申请号：US360730

申请日：1982-03-22

申请人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

发明人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

IPC分类号： H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82

CPC分类号： H01L27/0825 ,  H01L21/3065 ,  H01L21/8222 ,  H01L29/1004

摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.

摘要翻译： 描述了一种方法，其允许在集成电路芯片的选定区域中制造非常窄的基极宽度双极晶体管，并且在同一集成电路芯片的其它选定区域上制造宽基极宽度的双极晶体管。 将晶体管特性从集成电路芯片的一个区域选择性地变化到另一个区域的能力提供了有价值的集成电路设计的自由度。 使用常规技术将集成电路芯片上的双极晶体管加工成发射点形成点。 但是，在发射极形成之前，将使用反应离子蚀刻干法蚀刻作为具有非常窄的基极晶体管的选定区域的发射极的基极区域。 将其中具有发射极开口的现有氮化硅/二氧化硅层用作该反应离子蚀刻程序的蚀刻掩模。 一旦蚀刻完成到期望的深度，则恢复正常处理以形成发射器和金属化的其余部分。

公开(公告)号：US4409498A

公开(公告)日：1983-10-11

申请号：US221684

申请日：1980-12-30

申请人： Jack A. Dorler ,  Joseph M. Mosley

发明人： Jack A. Dorler ,  Joseph M. Mosley

IPC分类号： H03K19/018 ,  H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086 ,  H03K17/16 ,  H03K19/092

CPC分类号： H03K19/086 ,  H03K19/0136

摘要： A current controlled gate performing a NOR function utilizes a pair of transistors acting as current mirrors that receive a DC bias through a large resistor. This bias occurs when an input transistor is positive to insure that one of the current mirror transistors will saturate when the input transistors are "off" and the other will be driven into saturation when either of the input transistors is "on". When all inputs are negative, one of the current mirror transistors saturates thereby reducing the current to the input transistors effectively to zero. The saturation results in the collector-base capacitance increasing very rapidly such that the input assumes the characteristics of a common emitter due to the large capacitance existing in the collector of the current mirror transistor. An active push-pull output is produced with a single collector path from input to output.

摘要翻译： 执行NOR功能的电流控制栅极利用一对晶体管，其作为通过大电阻器接收DC偏置的电流镜。 当输入晶体管为正时，发生偏压，以确保当输入晶体管“截止”时电流镜晶体管中的一个将饱和，而当任一个输入晶体管“导通”时，另一个将被驱动为饱和。 当所有输入为负时，电流镜晶体管之一饱和，从而将输入晶体管的电流有效地降低到零。 饱和度导致集电极 - 基极电容非常快速地增加，使得由于存在于电流镜晶体管的集电极中的大电容，输入采用公共发射极的特性。 通过从输入到输出的单个收集器路径产生有源推挽输出。

公开(公告)号：US4829198A

公开(公告)日：1989-05-09

申请号：US37306

申请日：1987-04-10

申请人： Gerald A. Maley ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Gerald A. Maley ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/007

CPC分类号： H03K19/0075

摘要： A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.

公开(公告)号：US5032897A

公开(公告)日：1991-07-16

申请号：US486467

申请日：1990-02-28

申请人： Mohanlal S. Mansuria ,  Joseph M. Mosley ,  Richard D. Musa ,  William F. Shutler ,  Vito J. Tuozzolo

发明人： Mohanlal S. Mansuria ,  Joseph M. Mosley ,  Richard D. Musa ,  William F. Shutler ,  Vito J. Tuozzolo

IPC分类号： H01L23/38

CPC分类号： H01L23/38 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15174 ,  Y10S257/93

摘要： A thermoelectrically cooled integrated circuit package including an insulative module which defines a cavity, a thermoelectric cooler within the cavity, and an integrated circuit chip connected to the thermoelectric cooler, thus providing an integrated circuit package in which the integrated circuit package itself dissipates thermal energy generated by the integrated circuit chip.

公开(公告)号：US4689772A

公开(公告)日：1987-08-25

申请号：US792949

申请日：1985-10-30

申请人： George J. Jordy ,  Donald B. Mooney ,  Joseph M. Mosley

发明人： George J. Jordy ,  Donald B. Mooney ,  Joseph M. Mosley

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  G11C11/40

CPC分类号： G11C29/50012 ,  G11C29/50 ,  G11C7/00 ,  G11C8/18

摘要： A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory is designed to utilize an externally generated address valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/reset latch and starts the memory. The addressed memory cells are sensed. When at least one memory cell has data at its output below a threshold, the data are said to be unstable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits are stable, a signal is sent to the set/reset latch to cause it to be reset. The resetting of the set/reset latch causes an output thereof to change state. This state change comprises the read complete signal which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.

摘要翻译： 公开了一种用于产生用于高速密集封装的单片存储器的读取完整信号的电路和方法。 存储器被设计为利用外部产生的地址有效信号，其指示存储器的地址有效。 地址有效信号的接收设置一个置位/复位锁存器并启动存储器。 感测寻址的存储单元。 当至少一个存储单元在其输出端具有低于阈值的数据时，数据被称为不稳定，然后将设置/复位锁存器调整为复位。 当所有感测电路感测到的数据稳定时，信号被发送到设定/复位锁存器，使其复位。 复位/复位锁存器的复位使其输出改变状态。 该状态改变包括用于确定存储器的读取周期时间的读完成信号，并且还可以用于存储器的诊断测试。

公开(公告)号：US06708203B1

公开(公告)日：2004-03-16

申请号：US09348218

申请日：1999-07-06

申请人： Michael G. Makar ,  Joseph M. Mosley ,  Tracy A. Tindall

发明人： Michael G. Makar ,  Joseph M. Mosley ,  Tracy A. Tindall

IPC分类号： G06F1516

CPC分类号： G06F3/0489 ,  Y10S707/99936

摘要： A method is illustrated in the flow diagram 100 of FIG. 1. A processor 1001 renders a message 1025 for the processor operator's education during times of processor latency 1015, such as dialing onto any network, such as the Internet. This wait time 1017 is normally non-productive, and therefore can be used in such a way as to be non-invasive. It is also understood that this time is short, so as to make other actions, such as getting up from the desk, not attractive. Finally, even if the wait time was, or became, very short, the present invention provides the first message 1025 to the process operator that has been filtered. This filtering is a balance of the message owner's willingness to out bid other messages, the time of the day, the location of the operator, and finally the operator's likes and dislikes.

摘要翻译： 在图1的流程图100中示出了一种方法。 处理器1001在处理器延迟1015的时间期间呈现用于处理器操作员的教育的消息1025，诸如拨号到诸如因特网的任何网络。 这种等待时间1017通常是非生产性的，因此可以以非侵入性的方式使用。 另据了解，这个时间很短，以便采取其他行动，例如从桌子起床，不吸引人。 最后，即使等待时间是或者变得非常短，本发明向被过滤的处理操作者提供了第一消息1025。 这种过滤是消息所有者愿意出价其他消息，一天中的时间，运营商的位置，以及最后的运营商的喜欢和不喜欢的平衡。