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12 条记录 (耗时 0.03 秒)

    Method and apparatus for forming low resistance lateral links in a semiconductor device
    3.
    发明授权
    Method and apparatus for forming low resistance lateral links in a semiconductor device 失效
    用于在半导体器件中形成低电阻横向连杆的方法和装置

    公开(公告)号：US4636404A

    公开(公告)日：1987-01-13

    申请号：US651230

    申请日：1984-09-17

    申请人： Jack I. Raffel ,  John A. Yasaitis ,  Glenn H. Chapman

    发明人： Jack I. Raffel ,  John A. Yasaitis ,  Glenn H. Chapman

    IPC分类号： H01L23/525 ,  B05D3/06 ,  B05D5/12 ,  B23K9/00

    CPC分类号： H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  Y10S148/14

    摘要： A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

    摘要翻译： 一种用于可靠地形成沉积在绝缘多晶硅或非晶硅层上的两个铝导体之间的低电阻链路的方法和装置，采用激光来桥接导体之间的横向间隙。 该装置和方法理想地适用于在大型随机存取存储器和复杂VLSI电路中使用冗余来实现缺陷回避。 与现有技术相比，只采用单一级别的金属并且导致更高的密度和更低的电容。 对于大约2到3微米的间隙宽度，可实现1至10欧姆范围内的电阻。

    Capacitor memory and methods for reading, writing, and fabricating capacitor memories
    4.
    发明授权
    Capacitor memory and methods for reading, writing, and fabricating capacitor memories 失效
    电容器存储器和用于读，写和制造电容器存储器的方法

    公开(公告)号：US4242736A

    公开(公告)日：1980-12-30

    申请号：US8551

    申请日：1979-02-01

    申请人： Jack I. Raffel ,  John A. Yasaitis

    发明人： Jack I. Raffel ,  John A. Yasaitis

    IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C11/4063 ,  H01L21/822 ,  H01L27/10 ,  H01L29/94 ,  G11C7/00

    CPC分类号： H01L27/101 ,  G11C11/22 ,  G11C11/24 ,  G11C11/4063 ,  H01L21/822 ,  H01L29/94 ,  H01L2924/0002

    摘要： An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.

    摘要翻译： 公开了一种改进的金属双绝缘体半导体电容器存储器。 存储器包含多个电容器单元，每个单元包括半导体衬底层和夹着两个绝缘体层的高电导率层。 掺杂衬底以在表面耗尽层中以与积累方向上的写入电压相当的电压提供雪崩击穿。 本发明还提供一种在不干扰相邻小区的情况下读取存储的信息的方法。 在磁滞回线的“平带”部分上施加一个小的可变电压，描述电容器存储器的电压 - 电容关系。 通过电容器的电流的改变或不存在改变电容器电池的状态。 还公开了制造存储器的方法。

    Reading capacitor memories with a variable voltage ramp
    6.
    发明授权
    Reading capacitor memories with a variable voltage ramp 失效
    用可变电压斜坡读取电容器存储器

    公开(公告)号：US4127900A

    公开(公告)日：1978-11-28

    申请号：US808068

    申请日：1977-06-20

    申请人： Jack I. Raffel ,  John A. Yasaitis

    发明人： Jack I. Raffel ,  John A. Yasaitis

    IPC分类号： G11C11/401 ,  G11C16/04 ,  H01L21/306 ,  H01L21/761 ,  H01L21/764 ,  H01L21/822 ,  H01L23/52 ,  H01L27/10 ,  G11C7/00 ,  G11C11/24

    CPC分类号： H01L27/101 ,  G11C16/0466 ,  H01L21/30608 ,  H01L21/761 ,  H01L21/764 ,  H01L21/822 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： An improved method for reading metal dual insulator semiconductor capacitor memories is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. According to the invention, a small variable voltage is applied across a selected cell or cells. The range of voltage includes a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. The unselected cells are maintained in a depletion state in which their capacitance is a minimum. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell.

    摘要翻译： 公开了一种用于读取金属双绝缘体半导体电容器存储器的改进方法。 存储器包含多个电容器单元，每个单元包括半导体衬底层和夹着两个绝缘体层的高电导率层。 掺杂衬底以在表面耗尽层中以与积累方向上的写入电压相当的电压提供雪崩击穿。 根据本发明，在所选择的单元或单元上施加小的可变电压。 电压范围包括描述电容器存储器的电压 - 电容关系的磁滞回线的“平带”部分。 未选择的电池保持在其电容最小的耗尽状态。 通过电容器的电流的改变或不存在改变电容器电池的状态。

    Recessed Germanium (Ge) Diode
    7.
    发明申请
    Recessed Germanium (Ge) Diode 审中-公开

    公开(公告)号：US20100151619A1

    公开(公告)日：2010-06-17

    申请号：US12712858

    申请日：2010-02-25

    申请人： John A. Yasaitis ,  Lawrence Jay Lowell

    发明人： John A. Yasaitis ,  Lawrence Jay Lowell

    IPC分类号： H01L31/18 ,  H01L21/20

    CPC分类号： H01L31/18 ,  H01L27/1443 ,  H01L31/074

    摘要： A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.

    Recessed Germanium (Ge) Diode
    8.
    发明申请
    Recessed Germanium (Ge) Diode 审中-公开
    嵌入锗（Ge）二极管

    公开(公告)号：US20100006961A1

    公开(公告)日：2010-01-14

    申请号：US12169825

    申请日：2008-07-09

    申请人： John A. Yasaitis ,  Lawrence Jay Lowell

    发明人： John A. Yasaitis ,  Lawrence Jay Lowell

    IPC分类号： H01L31/00 ,  H01L21/00

    CPC分类号： H01L31/18 ,  H01L27/1443 ,  H01L31/074

    摘要： A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.

    摘要翻译： 在硅（Si）衬底中的凹入的锗（Ge）区域中形成光电二极管。 Ge区域可以通过蚀刻穿过Si衬底上的钝化层并进入Si衬底然后通过选择性外延工艺在孔中生长Ge来制造。 Ge似乎在孔中比在Si或氧化物表面上选择性地生长更好。 Ge可以长出孔的钝化侧壁的一些或全部，以保形地填充孔，并产生与衬底表面近似齐平的凹陷Ge区域，而没有台面的特征倾斜面。 孔可以被蚀刻到足够深的位置，因此光电二极管足够厚以获得进入光电二极管的垂直，自由空间光的良好的耦合效率。

    Partially self-aligned metal contact process
    9.
    发明授权
    Partially self-aligned metal contact process 失效
    部分自对准金属接触过程

    公开(公告)号：US4722910A

    公开(公告)日：1988-02-02

    申请号：US867048

    申请日：1986-05-27

    申请人： John A. Yasaitis

    发明人： John A. Yasaitis

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/76 ,  H01L29/78 ,  H01L21/443 ,  H01L21/473

    CPC分类号： H01L21/76897

    摘要： In a semiconductor device fabrication process, the SILO (Sealed Interface Local Oxidation) field oxide formation process is used to provide essentially vertical sidewalls between the field oxide surface and active regions. After field oxide formation and doping of active regions, the device is conformally coated with an oxide layer, which is patterned by a conventional photomasking process to define contact holes. Contact holes are then anisotropically etched through the oxide layer to the active regions. Conformal coating of the vertical sidewalls insures that an oxide sidewall spacer remains where the contact holes intersect the field oxide. Finally, a metal contact layer is deposited in the contact holes. The sidewall spacer automatically spaces the metal contact from the edges of the active region, thereby preventing leakage to the substrate.

    摘要翻译： 在半导体器件制造工艺中，SILO（密封接口局部氧化）场氧化物形成工艺用于在场氧化物表面和有源区之间提供基本垂直的侧壁。 在场氧化物形成和掺杂活性区域之后，器件保形地涂覆有氧化物层，其通过常规光掩模工艺构图以限定接触孔。 接触孔然后通过氧化物层各向异性蚀刻到活性区域。 垂直侧壁的保形涂层确保了氧化物侧壁间隔物保留在接触孔与场氧化物相交的位置。 最后，金属接触层沉积在接触孔中。 侧壁间隔物使金属接触件从有源区域的边缘自动放置，从而防止对基板的泄漏。