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    Pulsed laser anneal process for transistors with partial melt of a raised source-drain
    2.
    发明授权
    Pulsed laser anneal process for transistors with partial melt of a raised source-drain 有权
    脉冲激光退火工艺用于具有部分熔化的源极 - 漏极的晶体管

    公开(公告)号：US09006069B2

    公开(公告)日：2015-04-14

    申请号：US13976822

    申请日：2011-12-19

    申请人： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

    发明人： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

    IPC分类号： H01L21/268 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    摘要： A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

    摘要翻译： 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    5.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US07226824B2

    公开(公告)日：2007-06-05

    申请号：US10918818

    申请日：2004-08-13

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    8.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US06800887B1

    公开(公告)日：2004-10-05

    申请号：US10405110

    申请日：2003-03-31

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L2980

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    9.
    发明申请
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 失效
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US20050014351A1

    公开(公告)日：2005-01-20

    申请号：US10918818

    申请日：2004-08-12

    申请人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    发明人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7842

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Sub-second annealing processes for semiconductor devices
    10.
    发明授权
    Sub-second annealing processes for semiconductor devices 有权
    半导体器件的次秒退火工艺

    公开(公告)号：US07892971B2

    公开(公告)日：2011-02-22

    申请号：US12164560

    申请日：2008-06-30

    申请人： Jack Hwang ,  Sridhar Govindaraju ,  Karson Knutson ,  Harold Kennel ,  Aravind Killampalli

    发明人： Jack Hwang ,  Sridhar Govindaraju ,  Karson Knutson ,  Harold Kennel ,  Aravind Killampalli

    IPC分类号： H01L21/44

    CPC分类号： H01L21/324 ,  H01L21/28518 ,  H01L29/665

    摘要： An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.

    摘要翻译： 描述用于半导体制造的退火方法和装置。 该方法和装置允许可以跨越热预算的退火，并且可以针对具体过程及其对应的激活能量进行定制。 在一些情况下，退火方法跨越约1毫秒至约1秒的时间范围。 该退火方法的一个实例包括二次退火方法，其中在自杀化处理期间实现镍管形成的减少。 在一些情况下，该方法和装置将亚秒级退火的快速加热速率与导热基板相结合，为硅晶片提供快速冷却。 因此，次秒退火方法的热预算可以跨越从常规RTP退火到闪光退火工艺（包括退火的持续时间，以及峰值温度）的范围。 描述其他实施例。