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    Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same
    1.
    发明授权
    Methods of forming fine patterns in integrated circuit devices and methods of manufacturing integrated circuit devices including the same 有权
    在集成电路器件中形成精细图案的方法以及包括其的集成电路器件的制造方法

    公开(公告)号：US08247291B2

    公开(公告)日：2012-08-21

    申请号：US13009298

    申请日：2011-01-19

    申请人： Jae-Ho Min ,  Young-Ju Park ,  Myeong-Cheol Kim

    发明人： Jae-Ho Min ,  Young-Ju Park ,  Myeong-Cheol Kim

    IPC分类号： H01L21/74

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11529

    摘要： A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.

    摘要翻译： 一种制造集成电路器件的方法包括在基片的相应的第一和第二区域的硬掩模层上形成第一和第二预掩模结构。 间隔件形成在第一和第二预掩模结构的相对侧壁上，并且第一预备掩模结构从第一区域中的间隔物之间​​选择性地去除。 使用间隔物和第二预备掩模结构作为掩模蚀刻硬掩模层，以限定包括在第一区域中具有空隙的相对的侧壁间隔物的第一掩模图案，以及包括相对的侧壁间隔件和第二掩模图案的第二掩模图案 在第二区域之间的初步掩模结构。 使用第一和第二掩模图案作为相应的掩模来图案化绝缘层，以限定第一区域中的第一沟槽和第二区域中的第二沟槽具有比第一沟槽更大的宽度，并且第一和第二导电图案形成在 第一和第二个沟渠。

    METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME
    2.
    发明申请
    METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME 有权
    在集成电路装置中形成精细图案的方法和制造包括其中的集成电路装置的方法

    公开(公告)号：US20110183505A1

    公开(公告)日：2011-07-28

    申请号：US13009298

    申请日：2011-01-19

    申请人： Jae-Ho Min ,  Young-Ju Park ,  Myeong-Cheol Kim

    发明人： Jae-Ho Min ,  Young-Ju Park ,  Myeong-Cheol Kim

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11529

    摘要： A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.

    摘要翻译： 一种制造集成电路器件的方法包括在基片的相应的第一和第二区域的硬掩模层上形成第一和第二预掩模结构。 间隔件形成在第一和第二预掩模结构的相对侧壁上，并且第一预备掩模结构从第一区域中的间隔物之间​​选择性地去除。 使用间隔物和第二预备掩模结构作为掩模蚀刻硬掩模层，以限定包括在第一区域中具有空隙的相对的侧壁间隔物的第一掩模图案，以及包括相对的侧壁间隔件和第二掩模图案的第二掩模图案 在第二区域之间的初步掩模结构。 使用第一和第二掩模图案作为相应的掩模来图案化绝缘层，以限定第一区域中的第一沟槽和第二区域中的第二沟槽具有比第一沟槽更大的宽度，并且第一和第二导电图案形成在 第一和第二个沟渠。

    Methods of Forming Fine Patterns in Semiconductor Devices
    5.
    发明申请
    Methods of Forming Fine Patterns in Semiconductor Devices 有权
    在半导体器件中形成精细图案的方法

    公开(公告)号：US20120034784A1

    公开(公告)日：2012-02-09

    申请号：US13242504

    申请日：2011-09-23

    申请人： Jae-Ho Min ,  O-lk Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

    发明人： Jae-Ho Min ,  O-lk Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

    IPC分类号： H01L21/308

    CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

    摘要翻译： 形成半导体器件的方法可以包括提供具有第一区域和第二区域的特征层。 所述方法还可以包括在特征层上形成双掩模层。 所述方法还可以包括在双掩模层上形成可变掩模层。 所述方法还可以包括通过对可变掩模层和双掩模层进行构图来在第一区域中的特征层上形成第一结构和在第二区域中的特征层上形成第二结构。 所述方法还可以包括在第一结构的侧壁上形成第一间隔物，在第二结构的侧壁上形成第二间隔物。 所述方法还可以包括在保持第二结构的至少一部分的同时移除第一结构。

    METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES
    8.
    发明申请
    METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES 审中-公开
    在半导体器件中形成精细图案的方法

    公开(公告)号：US20140328125A1

    公开(公告)日：2014-11-06

    申请号：US14334984

    申请日：2014-07-18

    申请人： Jae-Ho Min ,  O-lk Kwon ,  Bum-Soo Kim ,  Dong-Chan Kim ,  Myeong-Cheol Kim

    发明人： Jae-Ho Min ,  O-lk Kwon ,  Bum-Soo Kim ,  Dong-Chan Kim ,  Myeong-Cheol Kim

    IPC分类号： G11C16/04 ,  G11C5/06

    CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

    摘要翻译： 形成半导体器件的方法可以包括提供具有第一区域和第二区域的特征层。 所述方法还可以包括在特征层上形成双掩模层。 所述方法还可以包括在双掩模层上形成可变掩模层。 所述方法还可以包括通过对可变掩模层和双掩模层进行构图来在第一区域中的特征层上形成第一结构和在第二区域中的特征层上形成第二结构。 所述方法还可以包括在第一结构的侧壁上形成第一间隔物，在第二结构的侧壁上形成第二间隔物。 所述方法还可以包括在保持第二结构的至少一部分的同时移除第一结构。

    Method of forming a dielectric layer pattern and method of manufacturing a non-volatile memory device using the same
    10.
    发明授权
    Method of forming a dielectric layer pattern and method of manufacturing a non-volatile memory device using the same 失效
    形成电介质层图案的方法和使用其制造非易失性存储器件的方法

    公开(公告)号：US07727893B2

    公开(公告)日：2010-06-01

    申请号：US12336863

    申请日：2008-12-17

    申请人： Jae-Ho Min ,  Dong-Hyun Kim

    发明人： Jae-Ho Min ,  Dong-Hyun Kim

    IPC分类号： H01L21/311

    CPC分类号： H01L27/115 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31122 ,  H01L27/11521

    摘要： In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed.

    摘要翻译： 在形成电介质层图案的方法中，在基板上形成下图案。 第一电介质层形成在下图案的侧壁和上表面以及基板的表面上。 在第一电介质层上形成掩模图案以部分地暴露第一介电层。 部分地去除在下图案的上表面和上侧壁上的暴露的第一电介质层，并且将去除的第一介电层沉积在下图案之间的第一介电层的表面上，以形成厚度大于其的厚度的第二电介质层。 的第一介电层。 在下图案和衬底的侧壁上的第二电介质层被蚀刻以形成电介质层图案。 因此，可能减少对下层的损伤，并且可以完全去除不需要的介电层。