公开(公告)号：US20120313067A1

公开(公告)日：2012-12-13

申请号：US13463244

申请日：2012-05-03

申请人： Jaekyu LEE ,  Kiseok Suh ,  Tae Eung Yoon

发明人： Jaekyu LEE ,  Kiseok Suh ,  Tae Eung Yoon

IPC分类号： H01L45/00

CPC分类号： H01L45/1691 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1641

摘要： A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.

摘要翻译： 存储器件包括半导体衬底中的下互连，下互连由不同于半导体衬底的材料制成，下互连上的选择元件以及选择元件上的存储元件。

公开(公告)号：US08614433B2

公开(公告)日：2013-12-24

申请号：US13463244

申请日：2012-05-03

申请人： Jaekyu Lee ,  Kiseok Suh ,  Tae Eung Yoon

发明人： Jaekyu Lee ,  Kiseok Suh ,  Tae Eung Yoon

IPC分类号： H01L45/00

CPC分类号： H01L45/1691 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1641

摘要： A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.

摘要翻译： 存储器件包括半导体衬底中的下互连，下互连由不同于半导体衬底的材料制成，下互连上的选择元件以及选择元件上的存储元件。

公开(公告)号：US09806028B2

公开(公告)日：2017-10-31

申请号：US14791812

申请日：2015-07-06

申请人： Jaekyu Lee ,  Kiseok Suh

发明人： Jaekyu Lee ,  Kiseok Suh

IPC分类号： H01L23/535 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L27/108

CPC分类号： H01L23/535 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.

公开(公告)号：US20150294695A1

公开(公告)日：2015-10-15

申请号：US14609977

申请日：2015-01-30

申请人： Jaekyu Lee ,  Kiseok Suh

发明人： Jaekyu Lee ,  Kiseok Suh

IPC分类号： G11C5/08 ,  G11C5/02 ,  G11C11/16

CPC分类号： G11C11/165 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/025 ,  G11C2213/52 ,  G11C2213/79 ,  G11C2213/82

摘要： A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments.

摘要翻译： 磁存储器件可以包括被配置为存储数据的多个单独可控的磁存储器段。 多个单独可控的源极线可以各自耦合到多个可分开控制的磁存储器段中的相应一个。

公开(公告)号：US10283698B2

公开(公告)日：2019-05-07

申请号：US15666903

申请日：2017-08-02

申请人： Seung Pil Ko ,  Kiseok Suh ,  Kilho Lee ,  Daeeun Jeong

发明人： Seung Pil Ko ,  Kiseok Suh ,  Kilho Lee ,  Daeeun Jeong

IPC分类号： H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/08 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12 ,  H01L23/485 ,  H01L23/532

摘要： A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.

公开(公告)号：US08481426B2

公开(公告)日：2013-07-09

申请号：US13029449

申请日：2011-02-17

申请人： Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

发明人： Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

IPC分类号： H01L21/44 ,  H01L21/461 ,  H01L21/302 ,  H01L21/311 ,  H01L21/469

CPC分类号： H01L27/24 ,  H01L21/31144

摘要： A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

摘要翻译： 提供一种形成图案结构的方法和使用该图案结构制造半导体器件的方法，形成图案结构的方法包括在形成在下层上的下层上形成掩模。 使用掩模作为蚀刻掩模蚀刻下层，从而在下层上形成图案。 模式至少定义一个开口。 在开口中形成牺牲层，并且去除掩模。 当去除掩模时，开口中的牺牲层被部分蚀刻。

公开(公告)号：US10164170B2

公开(公告)日：2018-12-25

申请号：US15622064

申请日：2017-06-13

申请人： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

发明人： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L27/22

摘要： A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

公开(公告)号：US20120264273A1

公开(公告)日：2012-10-18

申请号：US13421280

申请日：2012-03-15

申请人： YounSeon KANG ,  Youngkuk Kim ,  Kiseok Suh

发明人： YounSeon KANG ,  Youngkuk Kim ,  Kiseok Suh

IPC分类号： H01L21/02

CPC分类号： H01L45/06 ,  H01L27/2472 ,  H01L45/141 ,  H01L45/1683

摘要： Semiconductor devices and methods of fabricating a semiconductor device are provided. The method includes forming a conductive region in a substrate and forming a dielectric layer on the substrate including the conductive region. The dielectric layer has an opening that exposes the conductive region. A buffer semiconductor pattern having a single crystalline state is formed on the exposed conductive region. A filling semiconductor pattern is formed in the opening using an epitaxial process that employs the single crystalline buffer semiconductor pattern as a seed layer. Related devices are also provided.

摘要翻译： 提供了制造半导体器件的半导体器件和方法。 该方法包括在衬底中形成导电区域，并在包括导电区域的衬底上形成电介质层。 电介质层具有露出导电区域的开口。 在暴露的导电区域上形成具有单晶状态的缓冲半导体图案。 使用采用单晶缓冲半导体图案作为种子层的外延工艺在开口中形成填充半导体图案。 还提供了相关设备。

公开(公告)号：US09711716B2

公开(公告)日：2017-07-18

申请号：US15246519

申请日：2016-08-24

申请人： Myoungsu Son ,  Kiseok Suh ,  Gwanhyeob Koh ,  KyungTae Nam ,  Yoonjong Song

发明人： Myoungsu Son ,  Kiseok Suh ,  Gwanhyeob Koh ,  KyungTae Nam ,  Yoonjong Song

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L27/224 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： A magnetic memory device and a method for manufacturing the magnetic memory device are disclosed. The method includes forming a first interlayer insulating layer on a substrate, forming a first conductive pattern that penetrates the first interlayer insulating layer, forming a mold insulating layer that includes first and second mold insulating layers on the first interlayer insulating layer, forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer, and forming a magnetic tunnel junction pattern on the second conductive pattern. The first mold insulating layer is in contact with the first conductive pattern, and the second mold insulating layer is disposed on the first mold insulating layer.

公开(公告)号：US20110207285A1

公开(公告)日：2011-08-25

申请号：US13029449

申请日：2011-02-17

申请人： Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

发明人： Jung-In Kim ,  Jaehee Oh ,  Kiseok Suh

IPC分类号： H01L21/02 ,  H01L21/027

CPC分类号： H01L27/24 ,  H01L21/31144

摘要： A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

摘要翻译： 提供一种形成图案结构的方法和使用该图案结构制造半导体器件的方法，形成图案结构的方法包括在形成在下层上的下层上形成掩模。 使用掩模作为蚀刻掩模蚀刻下层，从而在下层上形成图案。 模式至少定义一个开口。 在开口中形成牺牲层，并且去除掩模。 当去除掩模时，开口中的牺牲层被部分蚀刻。