公开(公告)号：US08625016B2

公开(公告)日：2014-01-07

申请号：US12958799

申请日：2010-12-02

申请人： Eric Fossum ,  Suk Pil Kim ,  Yoon Dong Park ,  Hoon Sang Oh ,  Hyung Jin Bae ,  Tae Eung Yoon

发明人： Eric Fossum ,  Suk Pil Kim ,  Yoon Dong Park ,  Hoon Sang Oh ,  Hyung Jin Bae ,  Tae Eung Yoon

IPC分类号： H04N5/335 ,  H01L31/062 ,  H01L21/02 ,  H01L21/00

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14641 ,  H01L31/103 ,  H04N5/374 ,  H04N5/3745 ,  H04N9/045 ,  H04N2209/047

摘要： Image sensors include a second photoelectric conversion device disposed in a lower portion of a substrate and a first photoelectric conversion device extending between the secondary photoelectric conversion device and a light receiving surface of the substrate. Electrical isolation between the first and second photoelectric conversion devices is provided by a photoelectron barrier, which may be an optically transparent electrically insulating material. MOS transistors may be utilized to transfer photoelectrons generated within the first and second photoelectric conversion devices to a floating diffusion region within the image sensor. These transistors may represent one example of means for transferring photoelectrons generated in the first and second photoelectric conversion devices to a floating diffusion region in the substrate, in response to first and second gating signals, respectively. The first and second gating signals may be active during non-overlapping time intervals.

摘要翻译： 图像传感器包括设置在基板的下部的第二光电转换装置和在二次光电转换装置和基板的光接收表面之间延伸的第一光电转换装置。 第一和第二光电转换装置之间的电隔离由光电子势垒提供，光电子势垒可以是光学透明的电绝缘材料。 可以使用MOS晶体管将在第一和第二光电转换装置内产生的光电子转移到图像传感器内的浮动扩散区域。 这些晶体管可以分别响应于第一和第二门控信号，表示用于将在第一和第二光电转换装置中产生的光电子转移到衬底中的浮动扩散区域的装置的一个示例。 第一和第二门控信号可以在非重叠时间间隔期间被激活。

公开(公告)号：US20120313067A1

公开(公告)日：2012-12-13

申请号：US13463244

申请日：2012-05-03

申请人： Jaekyu LEE ,  Kiseok Suh ,  Tae Eung Yoon

发明人： Jaekyu LEE ,  Kiseok Suh ,  Tae Eung Yoon

IPC分类号： H01L45/00

CPC分类号： H01L45/1691 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1641

摘要： A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.

摘要翻译： 存储器件包括半导体衬底中的下互连，下互连由不同于半导体衬底的材料制成，下互连上的选择元件以及选择元件上的存储元件。

公开(公告)号：US07986545B2

公开(公告)日：2011-07-26

申请号：US12465125

申请日：2009-05-13

申请人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

发明人： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/025

摘要： A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

摘要翻译： 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 耦合在多个位线和多个可变电阻之间的多个选择晶体管被设置。

公开(公告)号：US20110128430A1

公开(公告)日：2011-06-02

申请号：US12958799

申请日：2010-12-02

申请人： Eric Fossum ,  Suk Pil Kim ,  Yoon Dong Park ,  Hoon Sang Oh ,  Hyung Jin Bae ,  Tae Eung Yoon

发明人： Eric Fossum ,  Suk Pil Kim ,  Yoon Dong Park ,  Hoon Sang Oh ,  Hyung Jin Bae ,  Tae Eung Yoon

IPC分类号： H04N5/335 ,  H01L31/113 ,  H01L31/0232 ,  H01L31/00

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14641 ,  H01L31/103 ,  H04N5/374 ,  H04N5/3745 ,  H04N9/045 ,  H04N2209/047

摘要： Image sensors include a second photoelectric conversion device disposed in a lower portion of a substrate and a first photoelectric conversion device extending between the secondary photoelectric conversion device and a light receiving surface of the substrate. Electrical isolation between the first and second photoelectric conversion devices is provided by a photoelectron barrier, which may be an optically transparent electrically insulating material. MOS transistors may be utilized to transfer photoelectrons generated within the first and second photoelectric conversion devices to a floating diffusion region within the image sensor. These transistors may represent one example of means for transferring photoelectrons generated in the first and second photoelectric conversion devices to a floating diffusion region in the substrate, in response to first and second gating signals, respectively. The first and second gating signals may be active during non-overlapping time intervals.

摘要翻译： 图像传感器包括设置在基板的下部的第二光电转换装置和在二次光电转换装置和基板的光接收表面之间延伸的第一光电转换装置。 第一和第二光电转换装置之间的电隔离由光电子势垒提供，光电子势垒可以是光学透明的电绝缘材料。 可以使用MOS晶体管将在第一和第二光电转换装置内产生的光电子转移到图像传感器内的浮动扩散区域。 这些晶体管可以分别响应于第一和第二门控信号，表示用于将在第一和第二光电转换装置中产生的光电子转移到衬底中的浮动扩散区域的装置的一个示例。 第一和第二门控信号可以在非重叠时间间隔期间被激活。

公开(公告)号：US20090321878A1

公开(公告)日：2009-12-31

申请号：US12366151

申请日：2009-02-05

申请人： June-mo Koo ,  Suk-pil Kim ,  Tae-Eung Yoon

发明人： June-mo Koo ,  Suk-pil Kim ,  Tae-Eung Yoon

IPC分类号： H01L29/8605

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

摘要翻译： 提供了可以以堆叠结构进行扩展并因此可以高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 所述非易失性存储器件包括：至少一个第一电极，至少一个第二电极，与所述至少一个第一电极交叉，至少一个数据存储层插入在所述至少一个第一电极和所述第二电极之间的区域中 所述至少一个第一电极与所述至少一个第二电极交叉，并且所述至少一个金属硅化物层插入在所述至少一个第一电极和所述至少一个第二电极之间，所述至少一个第一电极在所述至少一个第一电极与 至少一个第二电极。

公开(公告)号：US20160308008A1

公开(公告)日：2016-10-20

申请号：US15060174

申请日：2016-03-03

申请人： KYOUNG HWAN YEO ,  Seonguk Park ,  Seungjae Lee ,  Doyoung Choi ,  Sunhom Steve Paak ,  Tae Eung Yoon ,  Dongho Cha ,  Ruiyi Chen

发明人： KYOUNG HWAN YEO ,  Seonguk Park ,  Seungjae Lee ,  Doyoung Choi ,  Sunhom Steve Paak ,  Tae Eung Yoon ,  Dongho Cha ,  Ruiyi Chen

IPC分类号： H01L29/40 ,  H01L27/11

CPC分类号： H01L29/408 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate electrode crossing the active pattern and a capping structure on the gate electrode. The capping structure includes first and second capping patterns that are sequentially stacked on the gate electrode. The second capping pattern completely covers a top surface of the first capping pattern, and a dielectric constant of the second capping pattern is greater than that of the first capping pattern.

摘要翻译： 提供了具有场效应晶体管的半导体器件。 半导体器件包括衬底，衬底上的有源图案，与有源图案交叉的栅电极和栅电极上的封盖结构。 封盖结构包括顺序地堆叠在栅电极上的第一和第二封盖图案。 第二封盖图案完全覆盖第一封盖图案的顶表面，并且第二封盖图案的介电常数大于第一封盖图案的介电常数。

公开(公告)号：US08124968B2

公开(公告)日：2012-02-28

申请号：US12366151

申请日：2009-02-05

申请人： June-mo Koo ,  Suk-pil Kim ,  Tae-Eung Yoon

发明人： June-mo Koo ,  Suk-pil Kim ,  Tae-Eung Yoon

IPC分类号： H01L29/08

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

摘要翻译： 提供了可以以堆叠结构进行扩展并因此可以高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 所述非易失性存储器件包括：至少一个第一电极，至少一个第二电极，与所述至少一个第一电极交叉，至少一个数据存储层插入在所述至少一个第一电极和所述第二电极之间的区域中 所述至少一个第一电极与所述至少一个第二电极交叉，并且所述至少一个金属硅化物层插入在所述至少一个第一电极和所述至少一个第二电极之间，所述至少一个第一电极在所述至少一个第一电极与 至少一个第二电极。

公开(公告)号：US07796432B2

公开(公告)日：2010-09-14

申请号：US12149213

申请日：2008-04-29

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2213/71

摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

摘要翻译： 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

公开(公告)号：US08120006B2

公开(公告)日：2012-02-21

申请号：US12585582

申请日：2009-09-18

申请人： Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

发明人： Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC分类号： H01L47/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.

摘要翻译： 提供了具有容易高度集成的堆叠结构的非易失性存储器件以及经济地制造非易失性存储器件的方法。 非易失性存储器件可以包括至少一个第一电极和至少一个彼此交叉的第二电极。 至少一个数据存储层可以设置在至少一个第一电极和至少一个第二电极彼此交叉的部分上。 所述至少一个第一电极可以包括第一导电层和第一半导体层。

公开(公告)号：US07948024B2

公开(公告)日：2011-05-24

申请号：US12484339

申请日：2009-06-15

申请人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo ,  Tae-eung Yoon

发明人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo ,  Tae-eung Yoon

IPC分类号： H01L21/336

CPC分类号： H01L27/11556 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

摘要： A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.

摘要翻译： 提供了一种非易失性存储装置，包括： 沿第一方向延伸的第一半导体层，与第一半导体层平行延伸并与第一半导体层分离的第二半导体层，在第一半导体层和第二半导体层之间的隔离层，第一半导体层与第一半导体层之间的第一半导体层， 所述隔离层，所述第二半导体层和所述隔离层之间的第二控制栅极电极，其中所述第二控制栅极电极和所述第一控制栅电极分别设置在所述隔离层的相对侧，所述第一控制栅极之间的第一电荷存储层 栅电极和第一半导体层，以及在第二控制栅电极和第二半导体层之间的第二电荷存储层。