公开(公告)号：US06847218B1

公开(公告)日：2005-01-25

申请号：US10144676

申请日：2002-05-13

申请人： James E. Nulty ,  Brenor L. Brophy ,  Thomas A. McCleary ,  Bo Jin ,  Qi Gu ,  Thurman J. Rodgers ,  John O. Torode

发明人： James E. Nulty ,  Brenor L. Brophy ,  Thomas A. McCleary ,  Bo Jin ,  Qi Gu ,  Thurman J. Rodgers ,  John O. Torode

IPC分类号： G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02 ,  G01R31/26

CPC分类号： G01R1/07378 ,  G01R1/07307

摘要： In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.

摘要翻译： 在一个实施例中，用于测试集成电路的环境包括耦合到测试器的第一管芯。 第一管芯包括被配置为将来自第一管芯的信号与适配器层耦合到被测试的第二管芯的可移除连接。 可移除连接可以是例如弹性体插入件或探针。

公开(公告)号：US07112975B1

公开(公告)日：2006-09-26

申请号：US10784566

申请日：2004-02-23

申请人： Bo Jin ,  James E. Nulty

发明人： Bo Jin ,  James E. Nulty

IPC分类号： G01R31/02

CPC分类号： G01R31/2889 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed.

摘要翻译： 在一个实施例中，抗晶片结构包括绝缘体上硅（SOI）层和形成在SOI层上的多个探针骰子。 每个探针管芯可以具有对应于待测晶片上的管芯的焊盘布局的焊盘布局。 多个孔可以延伸通过SOI层和多个探针骰子，每个孔对应于探针管芯上的焊盘。 反晶片结构可以有利地用于高级探针卡中。 还公开了用于制造抗晶片和高级探针卡的技术。

公开(公告)号：US07112974B1

公开(公告)日：2006-09-26

申请号：US10154089

申请日：2002-05-23

申请人： Bo Jin ,  Qi Gu

发明人： Bo Jin ,  Qi Gu

IPC分类号： G01R31/02

CPC分类号： G01R1/06711 ,  G01R1/06716 ,  G01R1/06738

摘要： In one embodiment, a probe for testing integrated circuits includes a body having a tip and a hardening material on the tip. The hardening material helps improve the hardness of the tip. The hardening material thus allows the probe to reliably penetrate a layer to make a good electrical connection with a contact point under the layer, for example. In one embodiment, an electrically conductive coating is deposited over the hardening material.

摘要翻译： 在一个实施例中，用于测试集成电路的探针包括具有尖端的主体和尖端上的硬化材料。 硬化材料有助于提高尖端的硬度。 因此，硬化材料允许探针可靠地穿透层，以与例如层之下的接触点形成良好的电连接。 在一个实施例中，导电涂层沉积在硬化材料上。

公开(公告)号：US06759865B1

公开(公告)日：2004-07-06

申请号：US10209088

申请日：2002-07-30

申请人： Qi Gu ,  Bo Jin

发明人： Qi Gu ,  Bo Jin

IPC分类号： G01R3126

CPC分类号： G01R31/2889

摘要： In one embodiment, a test interface for testing integrated circuits includes an array of dice. A removable electrical connection (e.g., an interposer) may be coupled between the array of dice and a wafer containing multiple dice to be tested. The removable electrical connection allows electrical signals to be transmitted between the array of dice and the wafer. The test interface may be used in conjunction with a tester.

摘要翻译： 在一个实施例中，用于测试集成电路的测试接口包括骰子阵列。 可拆卸的电连接（例如，插入件）可以连接在骰子阵列和包含待测试的多个骰子的晶片之间。 可拆卸电连接允许电信号在晶片阵列和晶片之间传输。 测试界面可以与测试仪一起使用。

公开(公告)号：US20240123420A1

公开(公告)日：2024-04-18

申请号：US17964316

申请日：2022-10-12

申请人： Kelly Nicholson ,  Bo Jin ,  Monica Zanfir

发明人： Kelly Nicholson ,  Bo Jin ,  Monica Zanfir

IPC分类号： B01J19/24 ,  C01B3/38 ,  C01B3/48

CPC分类号： B01J19/2415 ,  C01B3/384 ,  C01B3/48 ,  B01J2219/00103 ,  C01B2203/0233 ,  C01B2203/0811 ,  C01B2203/0894 ,  C01B2203/1241

摘要： The present disclosure relates to a furnace comprising:



a plurality of groupings, wherein each grouping in the furnace is adjacent to each other and separated by a gap, wherein each grouping comprises:
(a) one row of tubes and optionally additional rows of tubes comprising a plurality of tubes containing a catalyst for converting a gaseous feed, wherein each row of tubes is parallel to each other;
(b) at least two rows of burners comprising having a first and second row of outer burners and optionally additional rows of burners comprising a plurality of burners, and as described herein,
(c) wherein the plurality of burners within each grouping is configured such that the ratio of B/G is greater than 1.3 and the ratio of B/W is less than 1.3, wherein W, B and G are as defined herein.

公开(公告)号：US09102522B2

公开(公告)日：2015-08-11

申请号：US13434347

申请日：2012-03-29

申请人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick Jenne

发明人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick Jenne

IPC分类号： H01L21/336 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105

CPC分类号： B82Y10/00 ,  H01L21/28282 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

摘要翻译： 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域之上形成MOS器件的焊盘电介质层; 从半导体材料的薄膜形成存储器件的沟道，该半导体材料的薄膜覆盖在衬底的第二区域上方的表面，所述通道连接存储器件的源极和漏极; 形成覆盖在第二区域上方的通道上的图案化电介质堆叠，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，以及从衬底的第一区域去除焊盘介电层; 并且同时在衬底的第一区域上方形成栅极电介质层，并且在电荷俘获层上方形成阻挡电介质层。

公开(公告)号：US08718001B2

公开(公告)日：2014-05-06

申请号：US13497297

申请日：2010-06-30

申请人： Rong Zhang ,  Peng Hao ,  Bin Yu ,  Bo Jin ,  Peng Zhu ,  Yuxin Wang

发明人： Rong Zhang ,  Peng Hao ,  Bin Yu ,  Bo Jin ,  Peng Zhu ,  Yuxin Wang

IPC分类号： H04W72/04

CPC分类号： H04L1/0027 ,  H04L5/0048 ,  H04W72/042

摘要： A system and a method for allocating Sounding Reference Signal (SRS) resources are provided in the present invention, the method includes: an e-Node-B (eNB) allocating a SRS bandwidth with 4n Resource Blocks (RBs) to a terminal, and equally dividing a time domain sequence of a SRS into t portions in the SRS bandwidth; the eNB configuring a time domain RePetition Factor (RPF) used by the UE, and the eNB configuring the UE to use one or more cyclic shifts in L cyclic shifts for each UE; then the eNB notifying the UE of a value of the time domain RPF, a location of a used frequency comb and a used cyclic shift by signaling, wherein n is a positive integer; the RPF satisfies a following condition: 48 × n RPF can be exactly divided by 12; t is an integer by which 48 × n RPF can be exactly divided; and L≦t.

摘要翻译： 本发明提供了一种用于分配探测参考信号（SRS）资源的系统和方法，该方法包括：向终端分配具有4n个资源块（RB）的SRS带宽的e-Node-B（eNB），以及 将SRS的时域序列等分成SRS带宽中的t个部分; 所述eNB配置所述UE使用的时域RePetition Factor（RPF），所述eNB配置所述UE对每个UE使用L个循环移位中的一个或多个循环移位; 然后eNB通过UE通知信令的时域RPF的值，所使用的频率梳的位置和使用的循环移位，其中n是正整数; RPF满足以下条件：48×n RPF可以精确地除以12; t是48×n RPF可以精确分割的整数; 和L＆nlE; t。

公开(公告)号：US06808944B1

公开(公告)日：2004-10-26

申请号：US09621717

申请日：2000-07-24

申请人： Bo Jin ,  Kaichiu Wong

发明人： Bo Jin ,  Kaichiu Wong

IPC分类号： G01R3126

CPC分类号： H01L22/34

摘要： According to one embodiment, a structure for monitoring a process step may include an etch stop layer (102) formed on a substrate (104) and a trench emulation layer (106) formed over an etch stop layer (102). Monitor trenches (108) may be formed through a trench emulation layer (106) that terminate at an etch stop layer (102). Monitor trenches (108) may have a depth equal to a trench emulation layer (106) thickness. A trench emulation layer (106) thickness may be subject to less variation than a substrate trench depth. A monitor structure (100) may thus be used to monitor features formed by one or more process steps that may vary according to trench depth. Such process steps may include a shallow trench isolation insulator chemical mechanical polishing step. In addition, or alternatively, a monitor structure (100) may be formed on a non-semiconductor-on-insulator (SOI) wafer, but include SOI features, providing a less expensive alternative to monitoring some SOI process steps.

摘要翻译： 根据一个实施例，用于监测处理步骤的结构可以包括形成在衬底（104）上的蚀刻停止层（102）和形成在蚀刻停止层（102）上的沟槽仿真层（106）。 监测沟槽（108）可以通过终止在蚀刻停止层（102）处的沟槽仿真层（106）形成。 监视器沟槽（108）可以具有等于沟槽仿真层（106）厚度的深度。 沟槽仿真层（106）的厚度可能受到比衬底沟槽深度更小的变化。 因此，监视器结构（100）可用于监视由根据沟槽深度而变化的一个或多个处理步骤形成的特征。 这种工艺步骤可以包括浅沟槽隔离绝缘体化学机械抛光步骤。 另外或者替代地，可以在非半导体绝缘体（SOI）晶片上形成监视器结构（100），但是包括SOI特征，为监视一些SOI工艺步骤提供了较便宜的替代方案。

公开(公告)号：US20190031506A1

公开(公告)日：2019-01-31

申请号：US15658884

申请日：2017-07-25

申请人： Kelly Nicholson ,  Troy M. Raybold ,  Bo Jin

发明人： Kelly Nicholson ,  Troy M. Raybold ,  Bo Jin

IPC分类号： C01B3/38 ,  B01J8/06

摘要： The present invention relates to reactor tubes packed with a catalyst system employed to deliberately bias process gas flow toward the hot tube segment and away from the cold segment in order to reduce the circumferential tube temperature variation.

公开(公告)号：US09023707B1

公开(公告)日：2015-05-05

申请号：US13312964

申请日：2011-12-06

申请人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

发明人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC分类号： H01L21/336 ,  H01L21/768

CPC分类号： H01L21/768 ,  H01L27/11568 ,  H01L29/792

摘要： Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.

摘要翻译： 提供了ONO集成到MOS流中的方法。 在一个实施例中，该方法包括：（i）在衬底的MOS器件区域的上方形成焊盘电介质层; 并且（ii）在衬底的非易失性器件区域之上形成图案化的电介质堆叠，所述图案化的电介质叠层包括隧道层，电荷俘获层和牺牲顶层，所述电荷俘获层包括多个层，包括 形成在隧道层上的第一氮化物层和第二氮化物层，其中第一氮化物层相对于第二氮化物层富氧。 还描述了其它实施例。