公开(公告)号：US06847218B1

公开(公告)日：2005-01-25

申请号：US10144676

申请日：2002-05-13

申请人： James E. Nulty ,  Brenor L. Brophy ,  Thomas A. McCleary ,  Bo Jin ,  Qi Gu ,  Thurman J. Rodgers ,  John O. Torode

发明人： James E. Nulty ,  Brenor L. Brophy ,  Thomas A. McCleary ,  Bo Jin ,  Qi Gu ,  Thurman J. Rodgers ,  John O. Torode

IPC分类号： G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02 ,  G01R31/26

CPC分类号： G01R1/07378 ,  G01R1/07307

摘要： In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.

摘要翻译： 在一个实施例中，用于测试集成电路的环境包括耦合到测试器的第一管芯。 第一管芯包括被配置为将来自第一管芯的信号与适配器层耦合到被测试的第二管芯的可移除连接。 可移除连接可以是例如弹性体插入件或探针。

公开(公告)号：US06683468B1

公开(公告)日：2004-01-27

申请号：US09942436

申请日：2001-08-29

申请人： Brenor L. Brophy ,  James H. Lie ,  Andrew J. Wright

发明人： Brenor L. Brophy ,  James H. Lie ,  Andrew J. Wright

IPC分类号： G01R3102

CPC分类号： G01R31/2884 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0268 ,  H05K3/243 ,  H05K3/28 ,  H01L2924/00014

摘要： A ball grid array (BGA) package is disclosed. An interconnect structure is formed on a substrate that electrically connects the electrical device to be housed in the BGA package to the solder balls thereon. Contact pads are formed over the top surface of the substrate. These contact pads electrically connect to the interconnect structure. A layer of solder mask is formed over the substrate that includes openings that overlie the contact pads. The BGA is then completed using conventional process steps. Thereby, a BGA package is formed that includes contact pads disposed such that the contact pads are accessible from the top of the BGA package, making these contact pads easily accessible. Thus, when the BGA is attached to a circuit board, connection to circuits of the electrical device is obtainable.

摘要翻译： 公开了一种球栅阵列（BGA）封装。 在将要容纳在BGA封装中的电气装置电连接到其上的焊球的基板上形成互连结构。 接触垫形成在衬底的顶表面上。 这些接触垫电连接到互连结构。 在衬底上形成一层焊料掩模，该层包括覆盖接触焊盘的开口。 然后使用常规工艺步骤完成BGA。 由此，形成BGA封装，其包括布置成使得接触焊盘可从BGA封装的顶部接近的接触焊盘，使得这些接触焊盘容易接近。 因此，当BGA附接到电路板时，可以获得与电气装置的电路的连接。

公开(公告)号：US06918057B1

公开(公告)日：2005-07-12

申请号：US09939076

申请日：2001-08-24

申请人： Brenor L. Brophy ,  Xiao Ming Xi ,  Dinesh Nadavi

发明人： Brenor L. Brophy ,  Xiao Ming Xi ,  Dinesh Nadavi

IPC分类号： G06F11/00

CPC分类号： G01R31/318536 ,  G01R31/318555

摘要： Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and read/write operations can, therefore, be done after integrated circuits are populated upon a printed circuit board to control those integrated circuits using a standard JTAG interface, well-known as the IEEE Std. 1149.1 interface. A shift register used to control one or more electronic subcomponents can be programmed, written to, or read from using JTAG programming languages. However, the shift register, or multiple shift registers, used to control electronic subcomponents need not be JTAG compliant. The shift registers may be those found within proprietary circuits, such as analog-to-digital converters or digital-to-analog converters, and include any shift register than receives serial data and produces parallel data, or vice-versa, where the loading and serial shifting of data is controlled using a generic interface, such as enable, reset, capture, etc. One or more shift registers can be distributed among one or more integrated circuits proprietary to the manufacturer of that circuit, and the circuits which embody the shift registers need not have a JTAG interface. Yet, the shift registers can be controlled by a single test access port (TAP) external to the integrated circuits, but which controls the non-JTAG compliant shift registers of each integrated circuit bearing the same. This allows a JTAG programming language which can be readily obtained off-the-shelf to control integrated circuits which do not recognize JTAG control signals, nor do such integrated circuits necessarily have a JTAG four-pin interface.

摘要翻译： 提供了结构，电路和方法来编程，写入或读取可以布置在印刷电路板上的一个或多个集成电路。 因此，编程和读/写操作可以在集成电路填充在印刷电路板上之后进行，以使用标准的JTAG接口（众所周知的IEEE标准）控制这些集成电路。 1149.1接口。 用于控制一个或多个电子子部件的移位寄存器可以使用JTAG编程语言进行编程，写入或读取。 然而，用于控制电子子部件的移位寄存器或多个移位寄存器不需要符合JTAG。 移位寄存器可以是专有电路中的那些，例如模数转换器或数模转换器，并且包括任何移位寄存器，而不是接收串行数据，并产生并行数据，反之亦然，其中负载和 使用通用接口（如启用，复位，捕捉等）来控制数据的串行移位。一个或多个移位寄存器可以分配给该电路的制造商专有的一个或多个集成电路，并且实现移位的电路 寄存器不需要JTAG接口。 然而，移位寄存器可以由集成电路外部的单个测试访问端口（TAP）控制，但是控制与承载相同的每个集成电路的非JTAG兼容移位寄存器。 这允许可以容易地获得的JTAG编程语言来控制不识别JTAG控制信号的集成电路，也不需要这样的集成电路具有JTAG四引脚接口。

公开(公告)号：US06892337B1

公开(公告)日：2005-05-10

申请号：US09935283

申请日：2001-08-22

申请人： Brenor L. Brophy ,  Dinesh Nadavi

发明人： Brenor L. Brophy ,  Dinesh Nadavi

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/31715 ,  G01R31/318385

摘要： A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure. Instructions which begin and end the test operation are forwarded from a test device that is linked to the test system by a JTAG access port configured according to IEEE Std. 1149.1. This allows non-proprietary instructions to be sent into the access port controller, using only a single input pin among the four-pin JTAG access port, where a decoder within the test system is programmed to decode that instruction and either begin or end the test operation. A clock generation circuit will generate a high speed clock, for use by the physical device, to allow the physical device to operate at speed without requiring a costly test system to generate a high-speed clock and signals proprietary to that test system.

摘要翻译： 提供了一种用于测试物理层设备或连接到该物理层设备的各种网络部分的系统。 测试系统包括随机位产生器，其在使用期间产生并行时钟的位的随机模式到物理设备的发送部分上。 然后可以将并行馈送信息串行化并可选择地反馈到相同物理设备的接收输入。 然后，物理设备的接收部分可以对位的随机模式进行反序列化，并将这些位呈现给测试系统内的逻辑。 因此，测试系统可以将呈现给物理设备的位的随机模式与从解串器导出的相应位进行比较。 如果转发到串行器的m位的随机模式中的每个位都不与从解串器转发的每个对应的m位进行比较，则物理设备已知是故障的。 开始和结束测试操作的指令从通过根据IEEE Std配置的JTAG访问端口与测试系统链接的测试设备转发。 1149.1。 这允许将非专有指令发送到访问端口控制器，仅使用四引脚JTAG访问端口中的单个输入引脚，其中测试系统内的解码器被编程为对该指令进行解码并开始或结束测试 操作。 时钟发生电路将产生用于物理设备的高速时钟，以允许物理设备以高速运行，而不需要昂贵的测试系统来生成高速时钟，并且该测试系统专有信号。

公开(公告)号：US06649832B1

公开(公告)日：2003-11-18

申请号：US09944874

申请日：2001-08-31

申请人： Brenor L. Brophy ,  James H. Lie ,  Andrew J. Wright

发明人： Brenor L. Brophy ,  James H. Lie ,  Andrew J. Wright

IPC分类号： H05K506

CPC分类号： H01L23/04 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2924/00

摘要： An embodiment of the present invention provides a method and apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package, without high frequency signal degradation or other electrical problems. An embodiment of the present invention also provides a method and apparatus that effectuates testing access, directly to the internal die component of the surface mount package or to a particular circuit node or conductive trace locale of the surface mount package, enabling performance evaluation and system debugging. Further, an embodiment of the present invention provides a method and apparatus that effectuates integration of surface mount package with an opto-electronic package. Further still, an embodiment of the present invention provides a method and apparatus that achieves these advantages with minimal cost.

摘要翻译： 本发明的一个实施例提供一种方法和装置，其直接与内部管芯部件的单独构成子部件或表面安装封装的特定电路节点或导电迹线区域直接实现直接功能接口，而不会产生高频信号劣化或其他 电气问题。 本发明的一个实施例还提供了一种方法和装置，其实现了直接访问表面安装封装的内部管芯部件或表面安装封装的特定电路节点或导电迹线区域的测试访问，使得能够进行性能评估和系统调试 。 此外，本发明的实施例提供了一种实现表面贴装封装与光电封装集成的方法和装置。 此外，本发明的一个实施例提供了以最小的成本实现这些优点的方法和装置。

公开(公告)号：US07405474B1

公开(公告)日：2008-07-29

申请号：US11246361

申请日：2005-10-07

申请人： Brenor L. Brophy

发明人： Brenor L. Brophy

IPC分类号： H01L23/12

CPC分类号： H01L23/3675 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the substrate to allow heat to be conducted away from the backside of the die to a top most metal layer of the substrate. Thermal balls may be attached to the bottom side of the substrate on the same plane as the die.

摘要翻译： 在一个实施例中，使用低成本热增强球栅阵列（LCTE-BGA）封装封装器件。 该装置可以包括其背面安装到多层封装基板的底侧的裸片。 可以通过衬底形成热通孔，以允许热量从裸片的背面导出到衬底的最顶层金属层。 热球可以在与模具相同的平面上附着到基底的底侧。

公开(公告)号：US06592269B1

公开(公告)日：2003-07-15

申请号：US09944856

申请日：2001-08-31

申请人： Brenor L. Brophy ,  James H. Lie ,  Andrew J. Wright

发明人： Brenor L. Brophy ,  James H. Lie ,  Andrew J. Wright

IPC分类号： G02B636

CPC分类号： G02B6/4246 ,  G02B6/4253 ,  G02B6/4269 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/4283

摘要： An apparatus and method integrates optical transceivers for transfer of signals between optical and electronic media with surface mount packages, such as ball grid arrays and quad flat packs. A surface mount package is positioned directly beneath a modular optical transceiver. The surface mount package provides for electrically coupling external signals to the optical transceiver, so as to allow full performance functionality of data transfer components. An electrical coupling mechanism with high performance at high frequency is positioned between the surface mount package and the optical transceiver, electrically connecting them. In one implementation, the optical transceiver module is mounted directly to said surface mount package such that it is removable. In one embodiment, heat dissipation is provided by integral components and thermal vias, in addition to heat sinks. The apparatus, in one embodiment, allows optical transceivers to be modular and changeable, without connectors which can degrade high frequency signal transfer.

摘要翻译： 一种装置和方法集成了用于在光学和电子介质之间传输信号的光学收发器与诸如球栅阵列和四方扁平封装的表面贴装封装。 表面贴装封装位于模块化光收发器的正下方。 表面安装封装提供了将外部信号电耦合到光收发器，以便允许数据传输组件的全面性能功能。 在高频率下具有高性能的电耦合机构位于表面安装封装和光收发器之间，将它们电连接。 在一个实现中，光收发器模块直接安装到所述表面安装封装，使得其可移除。 在一个实施例中，除了散热器之外，散热由整体部件和热通孔提供。 在一个实施例中，该装置允许光收发器是模块化和可变的，而不会降低高频信号传输的连接器。