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公开(公告)号：US07494748B2
公开(公告)日：2009-02-24
申请号：US10904308
申请日：2004-11-03
IPC分类号： G03F1/00
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译： 用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。 原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。 形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。
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公开(公告)号：US06858889B2
公开(公告)日：2005-02-22
申请号：US09878117
申请日：2001-06-08
IPC分类号： H01L21/02 , H01L21/314 , H01L21/334 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译： 一种用于在半导体器件中形成电容器的工艺。 在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。
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3.发明授权Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor 失效具有大电容和低电阻的多晶硅电容器和用于形成电容器的工艺公开(公告)号：US06261895B1
公开(公告)日：2001-07-17
申请号：US09225043
申请日：1999-01-04
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译： 一种用于在半导体器件中形成电容器的工艺。 在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。
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公开(公告)号：US07669170B2
公开(公告)日：2010-02-23
申请号：US11676185
申请日：2007-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译： 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。
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公开(公告)号：US07188322B2
公开(公告)日：2007-03-06
申请号：US10906591
申请日：2005-02-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译： 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。
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公开(公告)号：US07361556B2
公开(公告)日：2008-04-22
申请号：US11495518
申请日：2006-07-31
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。
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公开(公告)号：US07112845B2
公开(公告)日：2006-09-26
申请号：US10064171
申请日：2002-06-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66818
摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.
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8.发明授权公开(公告)号：US06563131B1
公开(公告)日：2003-05-13
申请号：US09586501
申请日：2000-06-02
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Christopher S. Putnam , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Christopher S. Putnam , Jed H. Rankin
IPC分类号： H01L2906
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/66772 , H01L29/66787 , H01L29/78654
摘要： Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.
摘要翻译： 在栅极长度小于100纳米的场效应晶体管中，通过将导通沟道宽度保持为栅极长度的二分之一至四分之一，并将栅极定位在导电的至少两侧，不会损害截止电流 通道，从而创建一个完全耗尽的设备。 通过在最小光刻尺寸下形成槽，在槽内形成侧壁并蚀刻与侧壁自对准的栅极结构来实现这种窄导电沟道。 然后从槽中的源结构外延生长传导通道，使得源极，导电沟道和漏极区域是单一的单晶结构。
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9.发明授权Process for defining a pattern using an anti-reflective coating and structure therefor 失效使用抗反射涂层定义图案的方法及其结构
公开(公告)号：US06030541A
公开(公告)日：2000-02-29
申请号：US100542
申请日：1998-06-19
申请人： James W. Adkisson , Michael Caterer , James T. Marsh , Hung Ng , James M. Oberschmidt , Jed H. Rankin
发明人： James W. Adkisson , Michael Caterer , James T. Marsh , Hung Ng , James M. Oberschmidt , Jed H. Rankin
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/033
CPC分类号： H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removing the remaining portions of the photoresist layer and anti-reflective layer; and then patterning the substrate using the hard mask as the mask. Also provided is a structure for defining a pattern in a surface which comprises a surface having a hard mask material thereon; an anti-reflective coating located on the hard mask material; and a photoresist located on the anti-reflective coating. Also provided is an etchant composition for removing the hard mask material which comprises an aqueous composition of HF and chlorine.
摘要翻译： 通过在表面上提供硬掩模材料来限定表面中的图案; 在所述硬掩模材料上沉积抗反射涂层; 在抗反射涂层上施加光致抗蚀剂层; 图案化光致抗蚀剂层，抗反射层和硬掩模材料; 并除去光致抗蚀剂层和抗反射层的剩余部分; 然后使用硬掩模作为掩模来图案化衬底。 还提供了一种用于在表面上限定图案的结构，其包括其上具有硬掩模材料的表面; 位于硬掩模材料上的抗反射涂层; 以及位于抗反射涂层上的光致抗蚀剂。 还提供了用于除去硬掩模材料的蚀刻剂组合物，其包含HF和氯的水性组合物。
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公开(公告)号：US07915571B2
公开(公告)日：2011-03-29
申请号：US12646292
申请日：2009-12-23
申请人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。 不需要额外的引脚。
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