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    Multiple threshold voltage FET using multiple work-function gate materials
    2.
    发明授权
    Multiple threshold voltage FET using multiple work-function gate materials 失效
    多阈值电压FET采用多功能栅极材料

    公开(公告)号：US06448590B1

    公开(公告)日：2002-09-10

    申请号：US09695199

    申请日：2000-10-24

    申请人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    发明人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

    IPC分类号： H01L2710

    CPC分类号： H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

    摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

    摘要翻译： 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

    Method and structure of a dual/wrap-around gate field effect transistor
    5.
    发明授权
    Method and structure of a dual/wrap-around gate field effect transistor 有权
    双/环绕栅场效应晶体管的方法和结构

    公开(公告)号：US06563131B1

    公开(公告)日：2003-05-13

    申请号：US09586501

    申请日：2000-06-02

    申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

    发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Christopher S. Putnam ,  Jed H. Rankin

    IPC分类号： H01L2906

    CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78654

    摘要： Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.

    摘要翻译： 在栅极长度小于100纳米的场效应晶体管中，通过将导通沟道宽度保持为栅极长度的二分之一至四分之一，并将栅极定位在导电的至少两侧，不会损害截止电流 通道，从而创建一个完全耗尽的设备。 通过在最小光刻尺寸下形成槽，在槽内形成侧壁并蚀刻与侧壁自对准的栅极结构来实现这种窄导电沟道。 然后从槽中的源结构外延生长传导通道，使得源极，导电沟道和漏极区域是单一的单晶结构。