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公开(公告)号：US20090013519A1
公开(公告)日：2009-01-15
申请号：US12171106
申请日：2008-07-10
申请人： Jang Ho Park , Tae Hoon Kim , Jong Yeol Jeon
发明人： Jang Ho Park , Tae Hoon Kim , Jong Yeol Jeon
CPC分类号： H03H9/1021 , H01L21/50 , H01L23/10 , H01L24/94 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/16235 , Y10T29/42 , Y10T29/49005 , Y10T29/49007 , Y10T29/4908 , Y10T29/49147 , Y10T29/49155
摘要： A method for manufacturing a crystal device is provided. The method includes providing a package wafer including a plurality of internal and external connection terminals each having top and bottom ends respectively exposed to top and bottom surfaces of the package wafer; forming a height control member on the top end of the internal and external connection terminal and bonding one end of a crystal blank including an excitation electrode on the height control member; placing a bottom surface of a cap wafer having a cavity, which is open downward, on the top surface of the package wafer to which the crystal blank is mounted, and anodically bonding the package wafer with the cap wafer; and cutting the package wafer and the cap wafer in a direction across a bonding line formed by the bonding of the package wafer and the cap wafer to provide a plurality of crystal resonator that are individually separated.
摘要翻译： 提供一种晶体装置的制造方法。 该方法包括提供包括多个内部和外部连接端子的封装晶片，每个内部和外部连接端子各自具有分别暴露于封装晶片的顶部和底部表面的顶端和底端; 在所述内部和外部连接端子的顶端上形成高度控制构件，并将包括激励电极的晶体坯料的一端接合在所述高度控制构件上; 将具有在其上安装有晶体坯料的封装晶片的顶表面上的向下敞开的空腔的盖晶片的底表面放置，并且将封装晶片与盖晶片阳极接合; 并且沿着通过封装晶片和盖晶片的接合形成的接合线的方向切割封装晶片和盖晶片，以提供单独分离的多个晶体谐振器。
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公开(公告)号：US07845064B2
公开(公告)日：2010-12-07
申请号：US12171106
申请日：2008-07-10
申请人： Jang Ho Park , Tae Hoon Kim , Jong Yeol Jeon
发明人： Jang Ho Park , Tae Hoon Kim , Jong Yeol Jeon
IPC分类号： H04R31/00
CPC分类号： H03H9/1021 , H01L21/50 , H01L23/10 , H01L24/94 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/16235 , Y10T29/42 , Y10T29/49005 , Y10T29/49007 , Y10T29/4908 , Y10T29/49147 , Y10T29/49155
摘要： A control apparatus and method for controlling an image display includes at least one reference object for generating a predetermined spectrum signal, a modulation unit for modulating the predetermined spectrum signal with a predetermined method, and a remote controller. The remote controller includes an image sensor for receiving the modulated predetermined spectrum signal and generating a digital signal and a processing unit for receiving the digital signal, demodulating the digital signal, and calculating an image variation of the image of the reference object formed on the digital image.
摘要翻译： 用于控制图像显示的控制装置和方法包括用于产生预定频谱信号的至少一个参考对象，用于以预定方法调制预定频谱信号的调制单元和遥控器。 遥控器包括用于接收调制的预定频谱信号并产生数字信号的图像传感器和用于接收数字信号，解调数字信号以及计算形成在数字信号上的参考对象的图像的图像变化的处理单元 图片。
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公开(公告)号：US08222798B2
公开(公告)日：2012-07-17
申请号：US13223368
申请日：2011-09-01
申请人： Jong Beom Jeon , Katsushi Yasuda , Jong Pil Lee , Jang Ho Park
发明人： Jong Beom Jeon , Katsushi Yasuda , Jong Pil Lee , Jang Ho Park
IPC分类号： H01L41/08
CPC分类号： H03H3/04 , H03H9/02149 , H03H9/1021 , H03H9/131 , H03H2003/0428
摘要： There are provided an electrode structure of a piezoelectric resonator and a piezoelectric resonator including the same. The piezoelectric resonator includes: a piezoelectric plate vibrated by an electrical signal; and first and second electrodes having first to fourth layers stacked on both surfaces thereof, wherein the first and third layers are made of at least one selected from the group consisting of Ti, Ni, Cr, an alloy including Ti and an alloy including Cr and the second and fourth layers are made of Ag or an alloy including Ag.
摘要翻译： 提供了压电谐振器的电极结构和包括该电极结构的压电谐振器。 压电谐振器包括：通过电信号振动的压电板; 以及第一和第二电极，其两面层叠有第一至第四层，其中第一层和第三层由选自Ti，Ni，Cr，包括Ti和包括Cr和 第二层和第四层由Ag或包含Ag的合金制成。
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4.发明申请公开(公告)号：US20100079038A1
公开(公告)日：2010-04-01
申请号：US12428030
申请日：2009-04-22
申请人： Jong Beom Jeon , Katsushi Yasuda , Jong Pil Lee , Jang Ho Park
发明人： Jong Beom Jeon , Katsushi Yasuda , Jong Pil Lee , Jang Ho Park
IPC分类号： H01L41/047
CPC分类号： H03H9/02149 , H03H3/04 , H03H9/131 , H03H2003/0428
摘要： Provided are a piezoelectric vibrator and an electrode structure of the piezoelectric vibrator. The piezoelectric vibrator includes a piezoelectric material vibrating according to an electric signal, first and second electrode structures formed on the upper surface and the undersurface of the piezoelectric material, and including first to fourth layers sequentially stacked thereon, respectively. The first and third layers are formed of an alloy including Cr. The second and fourth layers are formed of Ag or an alloy including Ag.
摘要翻译： 提供压电振动器和压电振动器的电极结构。 压电振子包括根据电信号振动的压电材料，形成在压电材料的上表面和下表面上的第一和第二电极结构，并且分别包括依次层叠的第一至第四层。 第一和第三层由包括Cr的合金形成。 第二层和第四层由Ag或包含Ag的合金形成。
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5.发明申请公开(公告)号：US20090053439A1
公开(公告)日：2009-02-26
申请号：US12196108
申请日：2008-08-21
申请人： Jae Suk SUNG , Jang Ho Park , Young Suk Kim , Dae Seong Jeon , Kyongkeun Lee , Ha Ryong Hong
发明人： Jae Suk SUNG , Jang Ho Park , Young Suk Kim , Dae Seong Jeon , Kyongkeun Lee , Ha Ryong Hong
CPC分类号： H01Q1/243 , H01Q1/38 , H01Q9/0421 , Y10T156/1062 , Y10T428/1352 , Y10T428/24802 , Y10T428/24851
摘要： There are provided a film type antenna, a case structure using the same, and a method of manufacturing the same. A film type antenna according to aspect of the invention may include: a first polymer film; a decorative layer provided on one surface of the first polymer film; a second polymer film stacked on the decorative layer and having one surface in contact with the decorative layer; and an antenna pattern provided on the other surface of the second polymer film.
摘要翻译： 提供了一种薄膜型天线，使用该天线的壳体结构及其制造方法。 根据本发明的一个薄膜型天线可以包括：第一聚合物膜; 设置在第一聚合物膜的一个表面上的装饰层; 第二聚合物膜层叠在装饰层上并具有与装饰层接触的一个表面; 以及设置在第二聚合物膜的另一个表面上的天线图案。
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公开(公告)号：US08698593B2
公开(公告)日：2014-04-15
申请号：US13441596
申请日：2012-04-06
申请人： Jang Ho Park , Young Key Kim , Ki Won Suh , Jang Seok Yun , Jin Man Han , Sung Jun Kim
发明人： Jang Ho Park , Young Key Kim , Ki Won Suh , Jang Seok Yun , Jin Man Han , Sung Jun Kim
IPC分类号： H01C1/012
CPC分类号： H01C7/18 , H01C17/065 , H01C17/06526
摘要： There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).
摘要翻译： 提供了包括陶瓷基板的芯片电阻器; 形成在所述陶瓷基板上并且包括第一导电金属和第一玻璃的第一电阻层; 以及形成在第一电阻层上的第二电阻层，包括第二导电金属和第二玻璃，并且具有比第一电阻层更少的玻璃含量，从而获得相对低的电阻和相对较小的电阻温度系数（TCR ）。
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公开(公告)号：US08179226B2
公开(公告)日：2012-05-15
申请号：US12627111
申请日：2009-11-30
申请人： Heung Bok Ryu , Jang Ho Park , Young Key Kim , Ki Won Suh , Yun Gab Choi
发明人： Heung Bok Ryu , Jang Ho Park , Young Key Kim , Ki Won Suh , Yun Gab Choi
IPC分类号： H01C1/012
CPC分类号： H01C1/14 , H01C1/034 , H01C17/006 , H01C17/02
摘要： The present invention provides an array type chip resistor including: a substrate formed in a rectangular parallelepiped shape; lower electrodes disposed on both sides of a bottom surface of the substrate at equal spaces; side electrodes extended from some of lower electrodes, formed on outermost edges of both sides of the substrate, in all lower electrodes, to a side surface of the substrate; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.
摘要翻译： 本发明提供一种阵列式芯片电阻器，包括：形成为长方体形状的基板; 下部电极以等间隔设置在基板的底表面的两侧; 在基板的两侧的最外边缘上形成的一些下部电极在所有下部电极中延伸到基板的侧面的侧面电极; 插入在所述基板的底表面的下电极之间的电阻元件; 覆盖在所述电阻元件上的保护层，所述保护层具有覆盖所述下部电极的一部分和所述电阻元件的两侧; 调平电极与暴露于保护层外侧的下电极接触; 以及形成在平整电极上的镀层。 阵列型芯片电阻可以防止电阻元件在安装时由于外部冲击而被损坏，因为电阻元件被印刷在基板的底表面的下电极内部。
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公开(公告)号：US07095299B2
公开(公告)日：2006-08-22
申请号：US10854332
申请日：2004-05-27
申请人： Jeong Yub Lee , Jang Ho Park
发明人： Jeong Yub Lee , Jang Ho Park
CPC分类号： H03H9/14541 , H03H3/08 , H03H9/02929 , H03H9/02937 , Y10T29/42
摘要： In a fabrication method of a SAW device, a first conductive layer, an etch-stop layer made of conductive material and a second conductive layer are formed one atop another in order on a piezoelectric ceramic substrate. A mask is provided on a first portion of the second conductive layer corresponding to a first SAW filter. A second portion of the second conductive layer corresponding to a second SAW filter is selectively removed using the mask. The mask is removed and a photoresist pattern used for forming electrodes of the SAW filters is provided on the first portion of the second conductive layer corresponding to the first SAW filter region and on a first portion of the etch-stop layer corresponding to the second SAW filter region. The first and second conductive layers and the etch-stop layer are selectively removed using the photoresist pattern, and the photoresist pattern is then removed.
摘要翻译： 在SAW器件的制造方法中，在压电陶瓷衬底上依次形成第一导电层，由导电材料制成的蚀刻停止层和第二导电层。 在与第一SAW滤波器对应的第二导电层的第一部分上设置掩模。 使用掩模选择性地去除与第二SAW滤波器对应的第二导电层的第二部分。 去除掩模，并且在与第一SAW滤波器区域相对应的第二导电层的第一部分上和在对应于第二SAW滤波器区域的蚀刻停止层的第一部分上提供用于形成SAW滤波器的电极的光致抗蚀剂图案 过滤器区域。 使用光致抗蚀剂图案选择性地去除第一和第二导电层和蚀刻停止层，然后除去光致抗蚀剂图案。
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公开(公告)号：US08284016B2
公开(公告)日：2012-10-09
申请号：US12627577
申请日：2009-11-30
申请人： Heung Bok Ryu , Jang Ho Park , Young Key Kim , Ki Won Suh , Yun Gab Choi
发明人： Heung Bok Ryu , Jang Ho Park , Young Key Kim , Ki Won Suh , Yun Gab Choi
IPC分类号： H01C1/012
CPC分类号： H01C1/14 , H01C1/034 , H01C17/006 , H01C17/02
摘要： The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.
摘要翻译： 本发明提供了一种阵列型片式电阻器，包括：具有以相等间隔在其两侧形成的多个槽的衬底; 形成在基板的底面两侧的下电极; 上部电极形成在基板的顶表面的两侧; 电连接到上电极和下电极的侧电极; 插入在所述基板的底表面的下电极之间的电阻元件; 覆盖在所述电阻元件上的保护层，所述保护层具有覆盖所述下部电极的一部分和所述电阻元件的两侧; 调平电极与暴露于保护层外侧的下电极接触; 以及形成在平整电极上的镀层。 阵列型芯片电阻可以防止电阻元件在安装时由于外部冲击而被损坏，因为电阻元件被印刷在基板的底表面的下电极内部。
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公开(公告)号：US20110057765A1
公开(公告)日：2011-03-10
申请号：US12627577
申请日：2009-11-30
申请人： Heung Bok Ryu , Jang Ho Park , Young Key Kim , Ki Won Suh , Yun Gab Choi
发明人： Heung Bok Ryu , Jang Ho Park , Young Key Kim , Ki Won Suh , Yun Gab Choi
IPC分类号： H01C1/02
CPC分类号： H01C1/14 , H01C1/034 , H01C17/006 , H01C17/02
摘要： The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.
摘要翻译： 本发明提供了一种阵列型片式电阻器，包括：具有以相等间隔在其两侧形成的多个槽的衬底; 形成在基板的底面两侧的下电极; 上部电极形成在基板的顶表面的两侧; 电连接到上电极和下电极的侧电极; 插入在所述基板的底表面的下电极之间的电阻元件; 覆盖在所述电阻元件上的保护层，所述保护层具有覆盖所述下部电极的一部分和所述电阻元件的两侧; 调平电极与暴露于保护层外侧的下电极接触; 以及形成在平整电极上的镀层。 阵列型芯片电阻可以防止电阻元件在安装时由于外部冲击而被损坏，因为电阻元件被印刷在基板的底表面的下电极内部。
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