公开(公告)号：US08629012B2

公开(公告)日：2014-01-14

申请号：US13595797

申请日：2012-08-27

Applicant: Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

Inventor： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC: H01L21/338

CPC classification number: H01L29/205 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/122 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7783

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract translation: 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。

公开(公告)号：US08478091B2

公开(公告)日：2013-07-02

申请号：US13106072

申请日：2011-05-12

Applicant: Hung-Chih Lu ,  Jen-Inn Chyi

Inventor： Hung-Chih Lu ,  Jen-Inn Chyi

IPC: G02B6/34

CPC classification number: G02B6/29353

Abstract: A single-stage 1×5 grating-assisted wavelength division multiplexer is provided. A grating-assisted asymmetric Mach-Zehnder interferometer, a plurality of grating-assisted cross-state directional couplers and a plurality of novel side-band eliminators are combined to form the multiplexer. Only general gratings are required, not Bragg grating, for 5-channel wavelength division multiplexing in a single stage. A nearly ideal square-like band-pass filtering passband is obtained. The present disclosure can be used as a core device in IC-to-IC optical interconnects for multiplexing and demultiplexing of an optical transceiver. The present disclosure has a small size and good performance.

Abstract translation: 提供单级1×5光栅辅助波分复用器。 组合光栅辅助非对称马赫 - 策德尔干涉仪，多个光栅辅助交叉状态定向耦合器和多个新型侧带消除器以形成多路复用器。 只需要一般光栅，而不是布拉格光栅，用于单级5通道波分复用。 获得几乎理想的方形带通滤波通带。 本公开可以用作用于复用和解复用光收发器的IC至IC光互连中的核心设备。 本公开具有小尺寸和良好的性能。

公开(公告)号：US08426226B2

公开(公告)日：2013-04-23

申请号：US13342431

申请日：2012-01-03

Applicant: Jen-Inn Chyi ,  Geng-Yen Lee ,  Wei-Sheng Lin

Inventor： Jen-Inn Chyi ,  Geng-Yen Lee ,  Wei-Sheng Lin

IPC: H01L21/00

CPC classification number: H01L27/15

Abstract: A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.

Abstract translation: 一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。 由此，肖特基二极管经由金属层与LED电连接。 从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

公开(公告)号：US08101447B2

公开(公告)日：2012-01-24

申请号：US11961478

申请日：2007-12-20

Applicant: Hung-Cheng Lin ,  Chia-Ming Lee ,  Jen-Inn Chyi

Inventor： Hung-Cheng Lin ,  Chia-Ming Lee ,  Jen-Inn Chyi

IPC: H01L33/20

CPC classification number: H01L33/10 ,  H01L33/20

Abstract: The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby, an LED element having several inclines is obtained. Via the inclines, the probability of total internal reflection is reduced, and the light extraction efficiency of LED is promoted.

Abstract translation: 本发明公开了一种发光二极管（LED）元件及其制造方法，其可以提高LED的光提取效率，其中蚀刻基板以获得具有倾斜的自然晶体面的池，并且LED外延结构选择性地 形成在盆地内。 由此，得到具有多个倾斜的LED元件。 通过倾斜，全内反射的概率降低，LED的光提取效率得到提升。

公开(公告)号：US20110180846A1

公开(公告)日：2011-07-28

申请号：US12694002

申请日：2010-01-26

Applicant: Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

Inventor： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC: H01L27/092 ,  H01L29/20

CPC classification number: H01L29/205 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/122 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7783

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract translation: 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。

公开(公告)号：US07598105B2

公开(公告)日：2009-10-06

申请号：US11963517

申请日：2007-12-21

Applicant: Chia-Ming Lee ,  Hung-Cheng Lin ,  Jen-Inn Chyi

Inventor： Chia-Ming Lee ,  Hung-Cheng Lin ,  Jen-Inn Chyi

IPC: H01L21/00

CPC classification number: H01L33/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02647 ,  H01L21/02658 ,  H01L33/22

Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer. Next, the substrate is etched to form a plurality of concave zones and a plurality of convex zones with the chemical reaction layer overhead. Next, the chemical reaction layer is removed to form an irregular geometry of the concave zones and convex zones on the surface of the substrate. Then, a semiconductor light emitting structure is epitaxially formed on the surface of the substrate. Thereby, the present invention can achieve a light emitting diode structure having improved internal and external quantum efficiencies.

Abstract translation: 本发明公开了一种发光二极管结构及其制造方法。 在本发明中，将基板放置在溶液中以形成化学反应层。 接下来，蚀刻基板以形成具有化学反应层顶部的多个凹区域和多个凸区域。 接下来，去除化学反应层，以形成衬底表面上的凹区和凸区的不规则几何形状。 然后，在衬底的表面上外延形成半导体发光结构。 因此，本发明可以实现具有改善的内部和外部量子效率的发光二极管结构。

公开(公告)号：US07335523B2

公开(公告)日：2008-02-26

申请号：US11339251

申请日：2006-01-25

Applicant: Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

Inventor： Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

IPC: H01L21/00

CPC classification number: H01L33/507 ,  H01L25/0756 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device comprising a light-emitting unit including a plurality of first connecting pads, a base substrate including a plurality of second connecting pads, and a plurality of conductive bumps that connect the first connecting pads of the light-emitting unit to the second connecting pads of the base substrate. In the manufacturing process, a reflow process is performed to bond the conductive bumps to the first and second connecting pads. The light-emitting unit is configured to emit a first light radiation upon the application of an electric current flow, and the base substrate is configured to emit a second light radiation when stimulated by the first light radiation.

Abstract translation: 一种发光装置，包括包括多个第一连接焊盘的发光单元，包括多个第二连接焊盘的基板，以及将所述发光单元的第一连接焊盘连接到所述发光单元的多个导电凸块 基底基板的第二连接焊盘。 在制造过程中，执行回流处理以将导电凸块接合到第一和第二连接焊盘。 发光单元被配置为在施加电流时发射第一光辐射，并且基底基板被配置为当被第一光辐射刺激时发射第二光辐射。

公开(公告)号：US20080017100A1

公开(公告)日：2008-01-24

申请号：US11526067

申请日：2006-09-25

Applicant: Jen-Inn Chyi ,  Guan-Ting Chen

Inventor： Jen-Inn Chyi ,  Guan-Ting Chen

IPC: C30B23/00

CPC classification number: C30B23/02 ,  C30B25/02 ,  C30B29/16 ,  C30B29/403 ,  C30B29/406 ,  C30B29/605

Abstract: A GaN based substrate is obtained with a simple etching. The GaN based substrate is separate from another base substrate with the etching. The whole process is easy and costs low. The substrate is made of a material having a matching lattice length for a lattice structure so that the substrate has good characteristics. And the GaN based substrate has good heat dissipation so that the stability and life-time of GaN based devices on the GaN based substrate are enhanced even when they are constantly operated under a high power.

Abstract translation: 通过简单的蚀刻获得GaN基衬底。 基于GaN的衬底与另一个基底基板分离。 整个过程很简单，成本低廉。 衬底由具有格子结构匹配的晶格长度的材料制成，使得衬底具有良好的特性。 并且GaN基衬底具有良好的散热性，使得GaN基衬底上的GaN基器件的稳定性和寿命即使在高功率下不断运行时也能够提高。

公开(公告)号：US20050279990A1

公开(公告)日：2005-12-22

申请号：US10870347

申请日：2004-06-17

Applicant: Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

Inventor： Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

IPC: H01L29/06 ,  H01L33/38 ,  H01L33/46 ,  H01L33/62

CPC classification number: H01L33/38 ,  H01L33/46 ,  H01L33/62 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A light-emitting device comprises a multi-layer structure including one or more active layer configured to irradiate light in response to the application of an electric signal, a transparent passivation layer laid over an outmost surface of the multi-layer stack, a reflector layer laid over the passivation layer, and a plurality of electrode pads coupled with the multi-layer structure. In a manufacture process of the light-emitting device, the reflector layer and the passivation layer are patterned to form at least one opening exposing an area of the multi-layer structure. One electrode pad is formed through the opening of the reflector layer and the passivation layer to connect with the multi-layer structure

Abstract translation: 发光装置包括多层结构，其包括响应于电信号的施加而被配置为照射光的一个或多个有源层，布置在多层堆叠的最外表面上的透明钝化层，反射层 铺设在钝化层上，以及与多层结构耦合的多个电极焊盘。 在发光器件的制造工艺中，对反射层和钝化层进行构图以形成暴露多层结构区域的至少一个开口。 一个电极焊盘通过反射层的开口和钝化层形成，以与多层结构连接

公开(公告)号：US06514814B2

公开(公告)日：2003-02-04

申请号：US09884029

申请日：2001-06-20

Applicant: Cheng-Chung Jaing ,  Jyh-Shin Chen ,  Jen-Inn Chyi ,  Jeng-Jiing Sheu

Inventor： Cheng-Chung Jaing ,  Jyh-Shin Chen ,  Jen-Inn Chyi ,  Jeng-Jiing Sheu

IPC: H01L218242

CPC classification number: H01L28/56 ,  C23C14/088 ,  H01L28/60 ,  H01L28/75

Abstract: A preparation for forming a thin film capacitor includes forming an amorphous ferroelectric film, such as barium strontium titanate [(Ba,Sr)TiO3] film, for use as an interface between a metal electrode and a polycrystalline ferroelectric film, such as (Ba,Sr) TiO3 film. The polycrystalline ferroelectric film serves as a dielectric layer of the thin film capacitor in view of the fact that the polycrystalline ferroelectric film has a high dielectric constant. The amorphous ferroelectric film serves as a buffer layer for inhibiting the leakage current of the thin film capacitor. The amorphous ferroelectric film is grown by sputtering and by introducing a working gas, such as argon, and a reactive gas, such as oxygen, into a reaction chamber in which a plasma is generated at room temperature.

Abstract translation: 用于形成薄膜电容器的制备包括：形成诸如钛酸锶钡[（Ba，Sr）TiO 3]膜的非晶铁电体膜，用作金属电极和多晶铁电体膜之间的界面，例如（Ba， Sr）TiO3膜。 鉴于多晶强电介质膜具有高介电常数的事实，多晶铁电体膜用作薄膜电容器的电介质层。 非晶铁电体膜用作抑制薄膜电容器的漏电流的缓冲层。 通过溅射和诸如氩的工作气体和诸如氧的反应性气体引入到在室温下产生等离子体的反应室中生长非晶铁电膜。