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1.发明授权公开(公告)号：US06992387B2
公开(公告)日：2006-01-31
申请号：US10602096
申请日：2003-06-23
CPC分类号： H05K1/114 , H01G4/385 , H01L23/49838 , H01L23/642 , H01L2224/16 , H01L2224/16227 , H01L2924/00014 , H01L2924/01021 , H01L2924/01057 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K2201/09263 , H05K2201/09345 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2224/0401
摘要： According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
摘要翻译： 根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及 设置在所述第一导电平面和所述第二导电平面之间的电介质。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。
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2.发明授权公开(公告)号：US07211894B2
公开(公告)日：2007-05-01
申请号：US11103939
申请日：2005-04-12
IPC分类号： H01L23/48 , H01L27/108
CPC分类号： H05K1/114 , H01G4/385 , H01L23/49838 , H01L23/642 , H01L2224/16 , H01L2224/16227 , H01L2924/00014 , H01L2924/01021 , H01L2924/01057 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K2201/09263 , H05K2201/09345 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2224/0401
摘要： According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
摘要翻译： 根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面， 电介质设置在第一导电平面和第二导电平面之间，第三导电平面电耦合到第二端子并且不电耦合到第一端子，第二电介质设置在第二导电平面和第三导电平面之间。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。
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公开(公告)号：US07286368B2
公开(公告)日：2007-10-23
申请号：US10976716
申请日：2004-10-29
IPC分类号： H05K7/00
CPC分类号： H01L23/50 , H01L2224/16225 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/19106
摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.
摘要翻译： 根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。 集成电路封装可以包括多个导电触点和去耦电容器。 去耦电容器可以包括耦合到多个导电触点中的第一个的正极端子接触焊盘，正极端子接触焊盘包括第一基本上不导电的区域，以及耦合到多个导电触点中的第二个的负极端子接触焊盘 的导电触点，负极接触焊盘包括第二基本上不导电的区域。
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4.发明授权公开(公告)号：US07492605B2
公开(公告)日：2009-02-17
申请号：US11473359
申请日：2006-06-22
申请人： Yuan-Liang Li , Jayashree Kar , David G. Figueroa , Dong Zhong
发明人： Yuan-Liang Li , Jayashree Kar , David G. Figueroa , Dong Zhong
CPC分类号： H05K1/0265 , H05K1/0254 , H05K2201/044 , H05K2201/0784 , H05K2201/093 , H05K2201/0969
摘要： A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.
摘要翻译： 包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻 在电源插座和第二连接器电源插座之间。
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5.发明授权Circuit board with trace configuration for high-speed digital differential signaling 失效具有高速数字差分信号跟踪配置的电路板公开(公告)号：US06914334B2
公开(公告)日：2005-07-05
申请号：US10167904
申请日：2002-06-12
申请人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
发明人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
IPC分类号： H01L23/498 , H01L23/66 , H01P3/08 , H05K1/02 , H01L23/48
CPC分类号： H01P3/081 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H05K1/0242 , H05K1/0245 , H05K1/0265 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672 , H05K2201/0979 , H05K2201/098 , H05K2203/0733 , H01L2924/00
摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。
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6.发明授权Circuit board with trace configuration for high-speed digital differential signaling 失效具有高速数字差分信号跟踪配置的电路板公开(公告)号：US07417872B2
公开(公告)日：2008-08-26
申请号：US11459951
申请日：2006-07-26
申请人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
发明人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
IPC分类号： H05H1/11
CPC分类号： H01P3/081 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H05K1/0242 , H05K1/0245 , H05K1/0265 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672 , H05K2201/0979 , H05K2201/098 , H05K2203/0733 , H01L2924/00
摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有布置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。
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公开(公告)号：US07221046B2
公开(公告)日：2007-05-22
申请号：US10970237
申请日：2004-10-21
申请人： Dong Zhong , David G. Figueroa , Yuan-Liang Li
发明人： Dong Zhong , David G. Figueroa , Yuan-Liang Li
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/5386 , H01L24/17 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/14 , H01L2924/15312 , H01L2924/19106 , H05K1/0231 , H05K1/167 , H01L2924/00 , H01L2224/0401
摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one of the plurality of conductive contacts. The integrated circuit package may further include a decoupling capacitor having a plurality of capacitor pads, each of the plurality of capacitor pads being coupled to a respective one of the plurality of resistive portions.
摘要翻译： 根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。 集成电路封装可以包括多个导电触点，以及具有多个电阻部分的元件，多个电阻部分中的每一个耦合到多个导电触点中的相应一个。 集成电路封装还可以包括具有多个电容器焊盘的去耦电容器，所述多个电容器焊盘中的每一个耦合到所述多个电阻部分中的相应一个。
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公开(公告)号：US06784532B2
公开(公告)日：2004-08-31
申请号：US10209847
申请日：2002-07-31
申请人： Dong Zhong , Farzaneh Yahyaei-Moayyed , David G. Figueroa , Chris Baldwin , Jiangqi He , Yuan-Liang Li
发明人： Dong Zhong , Farzaneh Yahyaei-Moayyed , David G. Figueroa , Chris Baldwin , Jiangqi He , Yuan-Liang Li
IPC分类号： H01L2352
CPC分类号： H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.
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9.发明授权Circuit board with trace configuration for high-speed digital differential signaling 有权具有高速数字差分信号跟踪配置的电路板公开(公告)号：US07145239B2
公开(公告)日：2006-12-05
申请号：US10977192
申请日：2004-10-29
申请人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
发明人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
IPC分类号： H01L23/48
CPC分类号： H01P3/081 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H05K1/0242 , H05K1/0245 , H05K1/0265 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672 , H05K2201/0979 , H05K2201/098 , H05K2203/0733 , H01L2924/00
摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。
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公开(公告)号：US06964584B2
公开(公告)日：2005-11-15
申请号：US10032377
申请日：2001-12-21
申请人： Dong Zhong , Yuan-Liang Li , David G. Figueroa , Jiangqi He
发明人： Dong Zhong , Yuan-Liang Li , David G. Figueroa , Jiangqi He
IPC分类号： H01R13/6466 , H01R13/6473 , H01R13/66
CPC分类号： H01R13/6625 , H01R13/6466 , H01R13/6473
摘要： The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device. The capacitor may include plates that are vertically oriented relative to the major planar surface of the socket faces and capacitors may be located between a power and a ground contact, between two power contacts, or between two ground contacts.
摘要翻译： 本发明涉及一种用于微电子器件的电源插座，其在一个实施例中使用低电阻功率和接地端子配置。 在另一个实施例中，低电阻功率和接地端子配置结合在电源插座上，并具有用于降低电感的垂直取向的交叉指状电容器。 通过该组合，在微电子器件的操作期间实现显着降低的阻抗。 电容器可以包括相对于插座面的主平面垂直定向的板，并且电容器可以位于电源和接地触点之间，两个电源触点之间或两个接地触点之间。
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