公开(公告)号：US08328010B2

公开(公告)日：2012-12-11

申请号：US12593681

申请日：2007-03-27

申请人： Jeong Min Lee ,  Seong Jae Lee

发明人： Jeong Min Lee ,  Seong Jae Lee

IPC分类号： B65D85/08

CPC分类号： B65D51/2864 ,  B65D47/243

摘要： The storage chamber for secondary material applicable to the discharging direction of contents stored in the container consists of body with storage space and inseparable operating section mounted around the globe. If above operating section moves up, opening and closing hole made or formed in the storage space of storage is opened and contents stored in the storage space is dropped and mixed with contents stored in the container. The mixed contents are discharged via a vent mounted on the top of operating section. A vent is not opened until the operating section is opened, and closing section of opening and closing hole is provided so that the opening and closing hole may not be not clogged after being opened.

摘要翻译： 适用于储存在容器中的内容物的排放方向的二次材料储存室由具有储存空间的主体和安装在地球上的不可分离的操作部分组成。 如果上述操作部分向上移动，则打开储存空间中形成或形成的打开和关闭孔，并将存储在存储空间中的内容物与存储在容器中的内容物混合。 混合内容物通过安装在操作部分顶部的通风口排出。 在操作部分打开之前，排气口不会打开，并且设置打开和关闭孔的关闭部分，使得开启和关闭孔在打开之后不会被堵塞。

公开(公告)号：US20070029345A1

公开(公告)日：2007-02-08

申请号：US10584094

申请日：2004-11-05

申请人： Jeong Min Lee ,  Seong Jae Lee

发明人： Jeong Min Lee ,  Seong Jae Lee

IPC分类号： B67D5/60

CPC分类号： B01F3/12 ,  B01F15/0205 ,  B01F15/0215 ,  B01F15/0224 ,  B01F2215/0022 ,  B65D51/2835 ,  B65D51/2864 ,  B65D51/2878 ,  Y10S215/08

摘要： A structure for mixing different materials includes a main body having a lip portion with an upper opening portion, the main body coupled to an opening of a container containing a first material; a spouting guide member movably inserted in the lip portion by a predetermined distance; a cap ascending and descending together with the spouting guide member, the cap being coupled to the main body; and a seal closer separately formed on a lower portion of the spouting guide member.

摘要翻译： 用于混合不同材料的结构包括主体，其具有带有上开口部分的唇部，主体联接到容纳第一材料的容器的开口; 喷射引导构件，其可移动地插入所述唇部中预定距离; 与喷射引导构件一起上升和下降的盖，所述盖联接到所述主体; 以及分开形成在喷射引导构件的下部上的密封件。

公开(公告)号：US20070072336A1

公开(公告)日：2007-03-29

申请号：US11447820

申请日：2006-06-06

申请人： Han Young Yu ,  In Bok Baek ,  Chang Geun Ahn ,  Ki Ju Im ,  Jong Heon Yang ,  Ung Hwan Pi ,  Min Ki Ryu ,  Chan Woo Park ,  Sung Yool Choi ,  Seong Jae Lee

发明人： Han Young Yu ,  In Bok Baek ,  Chang Geun Ahn ,  Ki Ju Im ,  Jong Heon Yang ,  Ung Hwan Pi ,  Min Ki Ryu ,  Chan Woo Park ,  Sung Yool Choi ,  Seong Jae Lee

IPC分类号： H01L51/40 ,  C25D5/18

CPC分类号： H01L51/105 ,  B82Y10/00 ,  H01L51/0023 ,  H01L51/0595

摘要： Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.

摘要翻译： 提供一种制造纳米尺寸间隙电极器件的方法。 该方法包括以下步骤：在半导体层上设置浮动的纳米结构; 形成具有至少一个开口图案以与纳米结构相交的掩模层; 以及在通过所述开口图案暴露的所述半导体层上沉积金属以形成电极，使得通过所述纳米结构在所述纳米结构下方提供纳米尺寸间隙。

公开(公告)号：US08422314B2

公开(公告)日：2013-04-16

申请号：US13118287

申请日：2011-05-27

申请人： Seong Jae Lee

发明人： Seong Jae Lee

IPC分类号： G11C7/10

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4093

摘要： A method is provided for achieving SRAM output characteristics from DRAMs, in which a plurality of DRAMs are arranged connected in parallel to a controller in such a way as to be able to obtain SRAM output characteristics using the DRAMs, comprising a process in which data is output to an external device when a control signal for data reading has been input from the external device, by sequentially repeating a step in which the controller sends a data output state control signal to one DRAM and sends a refresh standby state control signal to the other DRAMs, the data is read and sent to the external device from the DRAM in the output state, and a refresh standby state control signal is sent to the DRAM which was in the output state while an output state control signal is sent to another DRAM and data is read out from the DRAM in the output state, and a step in which the controller sends a control signal for changing the output state to the refresh standby state.

摘要翻译： 提供了一种用于实现DRAM的SRAM输出特性的方法，其中以能够使用DRAM获得SRAM输出特性的方式将多个DRAM并行连接到控制器的方式，包括数据为 当从外部设备输入用于数据读取的控制信号时，通过依次重复控制器向一个DRAM发送数据输出状态控制信号并向另一个DRAM发送刷新待机状态控制信号的步骤，将其输出到外部设备 DRAM，在输出状态下从DRAM读取数据并将其发送到外部设备，并且将刷新待机状态控制信号发送到处于输出状态的DRAM，同时将输出状态控制信号发送到另一个DRAM， 在输出状态下从DRAM中读出数据，并且控制器将用于将输出状态改变为刷新待机状态的控制信号的步骤。

公开(公告)号：US07545000B2

公开(公告)日：2009-06-09

申请号：US11485837

申请日：2006-07-13

申请人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

发明人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

IPC分类号： H01L27/01

CPC分类号： H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US20080254606A1

公开(公告)日：2008-10-16

申请号：US12090891

申请日：2006-12-04

申请人： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

发明人： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

IPC分类号： H01L21/28

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L21/0273 ,  H01L21/28123 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7613 ,  H01L29/7831

摘要： Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.

摘要翻译： 提供了通过光刻处理改变光致抗蚀剂的特性以形成虚拟结构的半导体器件的制造方法，并且将该结构应用于形成栅电极的工艺。 该方法包括以下步骤：在半导体衬底的顶部上形成缓冲层; 在缓冲层上施加无机光致抗蚀剂，并使用光刻工艺形成光致抗蚀剂图案; 使用预定气体热处理光刻胶图案; 在热处理结构上均匀沉积绝缘层，并通过沉积的厚度蚀刻沉积层，以暴露热处理的光致抗蚀剂图案; 在蚀刻的结构上沉积绝缘层，并蚀刻沉积的绝缘层以暴露热处理的光致抗蚀剂图案; 使用蚀刻工艺去除曝光的光致抗蚀剂图案; 在除去光致抗蚀剂图案的部分中形成栅氧化层; 以及在所述栅极氧化物层上形成栅电极。 因此，在形成纳米尺寸器件的制造结构时，通过热处理提高了通过光刻工艺形成的层的性质，因此可以容易地形成用于制造各种器件的结构。

公开(公告)号：US20080125033A1

公开(公告)日：2008-05-29

申请号：US11944695

申请日：2007-11-26

申请人： Seong Jae Lee ,  Mi Ja Lee ,  Chang Soon Kim ,  Hyeong Soo Choi

发明人： Seong Jae Lee ,  Mi Ja Lee ,  Chang Soon Kim ,  Hyeong Soo Choi

IPC分类号： H04B7/14

CPC分类号： H04B7/15585

摘要： The present invention relates to a Radio Frequency Repeater to prevent oscillation with canceling a feedback interference signal between transmitting and receiving antenna with built-in transmitting and receiving antenna in wireless mobile communication repeater.A radio frequency repeater for canceling a feedback interference signal has a downlink path from a base station to a terminal and an uplink path from a terminal to a base station, and said downlink path and said uplink path is separated and combination by a duplexer.

摘要翻译： 本发明涉及一种无线电频率中继器，用于在无线移动通信中继器中利用内置发射和接收天线消除发射和接收天线之间的反馈干扰信号来防止振荡。 用于消除反馈干扰信号的射频中继器具有从基站到终端的下行链路路径和从终端到基站的上行链路路径，并且所述下行链路路径和所述上行链路路径被双工器分离并组合。

公开(公告)号：US07195962B2

公开(公告)日：2007-03-27

申请号：US10833452

申请日：2004-04-27

申请人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

发明人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L21/28114 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66772

摘要： Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.

摘要翻译： 提供了具有超短沟道长度的MOSFET及其制造方法。 超短沟道MOSFET具有三维结构的硅线沟道区，以及形成在由硅线沟道区的两侧形成的硅导电层中的源极/漏极结。 此外，包括在其间具有高介电常数的栅极绝缘层，以及连接到源极/漏极结的源极和漏极，形成在硅线沟道区的上表面上的栅电极。 通过利用取决于硅的平面取向的不同蚀刻速率，硅线沟道区域形成有三角形或梯形截面。 源极/漏极结通过固态扩散方法形成。

公开(公告)号：US06999772B2

公开(公告)日：2006-02-14

申请号：US10452633

申请日：2003-06-03

申请人： Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

发明人： Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

IPC分类号： H04Q7/20

CPC分类号： H04W72/0466 ,  H04B17/318 ,  H04B17/382 ,  H04B2201/70702 ,  H04W16/14 ,  H04W28/26 ,  H04W52/0206 ,  H04W72/02 ,  H04W72/0453 ,  H04W72/082 ,  H04W76/10 ,  H04W84/042 ,  Y02D70/00

摘要： A method for assigning a channel in multi-FA CDMA mobile communication system according to the received power prevents communication quality of a FA from being inferior to that of the others by managing the interference level of the FA. The method comprises the steps of: comparing a first threshold value with received power when the base station receives a new call request; assigning a traffic channel in a first FA of the request, if the received power is less than the first threshold value, and searching a second FA of which received power is least, if not; comparing a second threshold value with the received power of the second FA; and assigning a traffic channel in the second FA if the received power is less than the second threshold value, and rejecting the request, if not.

公开(公告)号：US06995452B2

公开(公告)日：2006-02-07

申请号：US10749749

申请日：2003-12-30

申请人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im

发明人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im

IPC分类号： H01L29/00

CPC分类号： H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused. Therefore, no crystal defect of a substrate is caused, thereby decreasing a junction leakage current.

摘要翻译： 提供了具有纳米级沟道的SOI MOSFET器件，其具有包括通过固相扩散形成的浅扩展区域和深结区域的源极/漏极区域以及SOI MOSFET器件的制造方法。 在制造MOSFET器件的方法中，使用掺杂有不同杂质的第一和第二氧化硅膜同时形成形成源/漏区的浅延伸区域和深结区域。 可以通过调整掺杂有第二杂质的第二氧化硅膜的厚度和蚀刻速率来缩小器件的有效沟道长度。 在形成栅电极之前，在衬底上形成源极/漏极区，从而容易地控制沟道中的杂质分布。 可以省略源极/漏极区域的杂质活化处理，从而防止器件的阈值电压的变化。 固相杂质扩散。 因此，不会引起衬底的晶体缺陷，从而减小结漏电流。