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    Ultra short channel field effect transistor and method of fabricating the same
    1.
    发明授权
    Ultra short channel field effect transistor and method of fabricating the same 有权
    超短沟道场效应晶体管及其制造方法

    公开(公告)号：US07195962B2

    公开(公告)日：2007-03-27

    申请号：US10833452

    申请日：2004-04-27

    申请人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

    发明人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78696 ,  H01L21/28114 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66772

    摘要： Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.

    摘要翻译： 提供了具有超短沟道长度的MOSFET及其制造方法。 超短沟道MOSFET具有三维结构的硅线沟道区，以及形成在由硅线沟道区的两侧形成的硅导电层中的源极/漏极结。 此外，包括在其间具有高介电常数的栅极绝缘层，以及连接到源极/漏极结的源极和漏极，形成在硅线沟道区的上表面上的栅电极。 通过利用取决于硅的平面取向的不同蚀刻速率，硅线沟道区域形成有三角形或梯形截面。 源极/漏极结通过固态扩散方法形成。

    MOSFET device with nanoscale channel and method of manufacturing the same
    2.
    发明授权
    MOSFET device with nanoscale channel and method of manufacturing the same 失效
    具有纳米级通道的MOSFET器件及其制造方法

    公开(公告)号：US06995452B2

    公开(公告)日：2006-02-07

    申请号：US10749749

    申请日：2003-12-30

    申请人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im

    发明人： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im

    IPC分类号： H01L29/00

    CPC分类号： H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

    摘要： Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused. Therefore, no crystal defect of a substrate is caused, thereby decreasing a junction leakage current.

    摘要翻译： 提供了具有纳米级沟道的SOI MOSFET器件，其具有包括通过固相扩散形成的浅扩展区域和深结区域的源极/漏极区域以及SOI MOSFET器件的制造方法。 在制造MOSFET器件的方法中，使用掺杂有不同杂质的第一和第二氧化硅膜同时形成形成源/漏区的浅延伸区域和深结区域。 可以通过调整掺杂有第二杂质的第二氧化硅膜的厚度和蚀刻速率来缩小器件的有效沟道长度。 在形成栅电极之前，在衬底上形成源极/漏极区，从而容易地控制沟道中的杂质分布。 可以省略源极/漏极区域的杂质活化处理，从而防止器件的阈值电压的变化。 固相杂质扩散。 因此，不会引起衬底的晶体缺陷，从而减小结漏电流。

    Method of manufacturing semiconductor device
    4.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07947585B2

    公开(公告)日：2011-05-24

    申请号：US12090891

    申请日：2006-12-04

    申请人： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

    发明人： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

    IPC分类号： H01L21/22

    CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L21/0273 ,  H01L21/28123 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7613 ,  H01L29/7831

    摘要： Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.

    摘要翻译： 提供了通过光刻处理改变光致抗蚀剂的特性以形成虚拟结构的半导体器件的制造方法，并且将该结构应用于形成栅电极的工艺。 该方法包括以下步骤：在半导体衬底的顶部上形成缓冲层; 在缓冲层上施加无机光致抗蚀剂，并使用光刻工艺形成光致抗蚀剂图案; 使用预定气体热处理光刻胶图案; 在热处理结构上均匀沉积绝缘层，并通过沉积的厚度蚀刻沉积层，以暴露热处理的光致抗蚀剂图案; 在蚀刻的结构上沉积绝缘层，并蚀刻沉积的绝缘层以暴露热处理的光致抗蚀剂图案; 使用蚀刻工艺去除曝光的光致抗蚀剂图案; 在除去光致抗蚀剂图案的部分中形成栅氧化层; 以及在所述栅极氧化物层上形成栅电极。 因此，在形成纳米尺寸器件的制造结构时，通过热处理提高了通过光刻工艺形成的层的性质，因此可以容易地形成用于制造各种器件的结构。

    Method of Manufacturing Semiconductor Device
    6.
    发明申请
    Method of Manufacturing Semiconductor Device 失效
    制造半导体器件的方法

    公开(公告)号：US20080254606A1

    公开(公告)日：2008-10-16

    申请号：US12090891

    申请日：2006-12-04

    申请人： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

    发明人： In Bok Baek ,  Seong Jae Lee ,  Jong Heon Yang ,  Chang Geun Ahn ,  Han Young Yu ,  Ki Ju Im

    IPC分类号： H01L21/28

    CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L21/0273 ,  H01L21/28123 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7613 ,  H01L29/7831

    摘要： Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.

    摘要翻译： 提供了通过光刻处理改变光致抗蚀剂的特性以形成虚拟结构的半导体器件的制造方法，并且将该结构应用于形成栅电极的工艺。 该方法包括以下步骤：在半导体衬底的顶部上形成缓冲层; 在缓冲层上施加无机光致抗蚀剂，并使用光刻工艺形成光致抗蚀剂图案; 使用预定气体热处理光刻胶图案; 在热处理结构上均匀沉积绝缘层，并通过沉积的厚度蚀刻沉积层，以暴露热处理的光致抗蚀剂图案; 在蚀刻的结构上沉积绝缘层，并蚀刻沉积的绝缘层以暴露热处理的光致抗蚀剂图案; 使用蚀刻工艺去除曝光的光致抗蚀剂图案; 在除去光致抗蚀剂图案的部分中形成栅氧化层; 以及在所述栅极氧化物层上形成栅电极。 因此，在形成纳米尺寸器件的制造结构时，通过热处理提高了通过光刻工艺形成的层的性质，因此可以容易地形成用于制造各种器件的结构。

    BIOSENSOR AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    BIOSENSOR AND METHOD OF MANUFACTURING THE SAME 有权
    生物传感器及其制造方法

    公开(公告)号：US20090152597A1

    公开(公告)日：2009-06-18

    申请号：US12195305

    申请日：2008-08-20

    申请人： Tae Youb KIM ,  Nae Man Park ,  Han Young Yu ,  Moon Gyu Jang ,  Jong Heon Yang

    发明人： Tae Youb KIM ,  Nae Man Park ,  Han Young Yu ,  Moon Gyu Jang ,  Jong Heon Yang

    IPC分类号： H01L29/12 ,  H01L21/00

    CPC分类号： G01N27/4146 ,  G01N27/4145 ,  Y10S977/71 ,  Y10S977/742 ,  Y10S977/963

    摘要： Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.

    摘要翻译： 本发明提供一种具有硅纳米线的生物传感器及其制造方法，更具体地，涉及具有通过电子束照射形成的缺陷区域的硅纳米线的生物传感器及其制造方法。 生物传感器包括：硅衬底; 设置在所述硅基板上的源极区域; 设置在所述硅基板上的漏极区域; 以及设置在源极区域和漏极区域上的硅纳米线，并且具有通过电子束的照射而形成的缺陷区域。 因此，通过用特定的区域照射具有电子束的高浓度掺杂的硅纳米线的特定区域来降低电子迁移率，可以保持硅纳米线与金属电极之间的低接触电阻并降低工作电流 的生物材料检测部件，从而提高生物传感器的灵敏度。