公开(公告)号：US06720258B2

公开(公告)日：2004-04-13

申请号：US10319313

申请日：2002-12-12

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

摘要翻译： 集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。 钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有 任何取向偏好，从而形成均匀的硅化镍层。 可以将镍硅化物退火以形成均匀的结晶二硅化镍。 因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

公开(公告)号：US06534871B2

公开(公告)日：2003-03-18

申请号：US09855391

申请日：2001-05-14

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2348

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

公开(公告)号：US07470573B2

公开(公告)日：2008-12-30

申请号：US11060878

申请日：2005-02-18

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L21/30 ,  H01L21/84

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/7842 ,  H01L29/78621

摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

摘要翻译： 在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

公开(公告)号：US07675056B2

公开(公告)日：2010-03-09

申请号：US11891574

申请日：2007-08-10

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113 ,  H01L31/0232

CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

摘要翻译： 提出了一种浮体锗（Ge）光电晶体管及其制造工艺。 该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

公开(公告)号：US20080280426A1

公开(公告)日：2008-11-13

申请号：US11801210

申请日：2007-05-09

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L29/739 ,  H01L21/20

CPC分类号： C30B29/406 ,  C30B25/183 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/267

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供（111）Si衬底并且在压缩覆盖Si衬底上形成第一含铝（Al）的膜。 在第一含Al膜中形成纳米柱孔，其暴露下面的Si衬底的区域。 从暴露区域选择性地生长GaN层，覆盖第一含Al膜。 使用横向纳米外延生长（LNEO）工艺生长GaN。 重复上述过程，在压缩中形成第二含Al膜，在第二含Al膜中形成纳米柱孔，并选择性地生长第二GaN层。 可以最初在低温下生长诸如Al 2 O 3 3，Si 1-x Ge x，InP，GaP，GaAs，AlN，AlGaN或GaN的膜材料。 通过增加生长温度，可以在Si衬底上形成外延GaN的压缩层。

公开(公告)号：US07351995B2

公开(公告)日：2008-04-01

申请号：US11894938

申请日：2007-08-22

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113 ,  H01L31/0232

CPC分类号： H01L31/1136

摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

摘要翻译： 提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。 该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。 在一个方面，第二S / D区域具有比第一S / D长度更长的长度。 光吸收阈值偏置区域位于第二S / D区域的下方。 或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

公开(公告)号：US06562703B1

公开(公告)日：2003-05-13

申请号：US10099374

申请日：2002-03-13

申请人： Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu ,  Jong-Jan Lee

发明人： Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu ,  Jong-Jan Lee

IPC分类号： H01L21265

CPC分类号： H01L21/263 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02694 ,  H01L29/1054 ,  Y10S438/933

摘要： A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si1−xGex) overlying the Si buffer layer having a thickness of 1000 to 5000 Å; implanting the Si1−xGex layer with ionized molecular hydrogen (H2+) a projected range of approximately 100 to 300 Å into the underlying Si buffer layer; optionally, implanting the Si1−xGex layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si1−xGex layer to a relaxed Si1−xGex layer. Optionally, after annealing, an additional layer of single-crystal Si1−xGex having a thickness of greater than 1000 Å can be deposited overlying the relaxed layer of Si1−xGex.

摘要翻译： 提供了一种在硅衬底上形成具有高锗含量的松弛硅锗层的方法。 该方法包括：沉积覆盖硅衬底的单晶硅（Si）缓冲层; 沉积覆盖厚度为1000至5000的Si缓冲层的单晶硅锗层（Si1-xGex）; 将具有离子化分子氢（H 2 +）的Si 1-x Ge x层投射到下面的Si缓冲层中约100至300埃的投影范围; 任选地，将Si1-xGex层用诸如硼，氦或硅的物质进行注入; 退火; 并且响应于退火，将Si1-xGex层转化为弛豫的Si1-xGex层。 任选地，在退火之后，可以沉积厚度大于的附加层的单晶Si1-xGex覆盖在Si1-xGex的松弛层上。

公开(公告)号：US07811913B2

公开(公告)日：2010-10-12

申请号：US11312967

申请日：2005-12-19

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/265

CPC分类号： H01L31/105 ,  H01L31/1808 ,  H01L31/1864 ,  Y02E10/50 ,  Y02P70/521 ,  Y10S438/933

摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

摘要翻译： 制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

公开(公告)号：US07651880B2

公开(公告)日：2010-01-26

申请号：US11592465

申请日：2006-11-04

申请人： Douglas J. Tweet ,  Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L25/00

CPC分类号： H01L31/1055 ,  H01L27/14643 ,  H01L27/14689

摘要： A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

摘要翻译： 提供锗（Ge）短波长红外（SWIR）成像器和相关制造工艺。 该成像器包括具有掺杂阱的硅（Si）衬底。 在位于Si衬底上的松弛的含Ge膜中形成一个pin二极管阵列，每个pin二极管具有倒装芯片接口。 存在Ge / Si界面和插入含Ge膜和Ge / Si界面之间的含掺杂Ge的缓冲层。 Si CMOS读出电路阵列结合到倒装芯片接口。 每个读出电路都具有零伏二极管偏置接口。

公开(公告)号：US20090173933A1

公开(公告)日：2009-07-09

申请号：US12236480

申请日：2008-09-23

申请人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L29/15

CPC分类号： H01L31/035254 ,  B82Y20/00 ,  H01L27/14649 ,  H01L31/028 ,  H01L31/101 ,  H01L31/1804 ,  Y02P70/521

摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

摘要翻译： 硅/锗（SiGe）超晶格热传感器具有相应的制造方法。 该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。 第一基板与第二基板接合，形成接合基板。 在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。