公开(公告)号：US06495469B1

公开(公告)日：2002-12-17

申请号：US09999309

申请日：2001-12-03

申请人： Jiing-Feng Yang ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Jiing-Feng Yang ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L21302

CPC分类号： H01L21/76807 ,  H01L21/0276 ,  H01L21/31116

摘要： A method for etching a dielectric layer comprising the following steps. A structure having a low-k dielectric layer formed thereover is provided. A DARC layer is formed over the low-k dielectric layer. A patterned masking layer is formed over the DARC layer. Using the patterned masking layer as a mask, the DARC layer and the low-k dielectric layer are etched employing an CHxFy/O2/N2/Ar etch chemistry.

摘要翻译： 一种用于蚀刻介电层的方法，包括以下步骤。 提供了一种其上形成有低k电介质层的结构。 在低k电介质层上形成DARC层。 在DARC层上形成图案化掩模层。 使用图案化掩模层作为掩模，使用CHxFy / O 2 / N 2 / Ar蚀刻化学法蚀刻DARC层和低k电介质层。

公开(公告)号：US06797630B1

公开(公告)日：2004-09-28

申请号：US10184735

申请日：2002-06-28

申请人： Tsang-Jiuh Wu ,  Chen-Nan Yeh ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Tsang-Jiuh Wu ,  Chen-Nan Yeh ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L21311

CPC分类号： H01L21/76811 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76813 ,  H01L2221/1021

摘要： A method for forming a dual damascene opening comprising the following steps. A structure having an exposed conductive structure formed therein is provided. An etch stop layer is formed over the structure and the exposed conductive structure. A dielectric layer is formed over the etch stop layer. A hard mask layer is formed over the dielectric layer. The hard mask layer is patterned to form a partially opened hard mask layer. The partially opened hard mask layer having a trench area and a via area. The partially opened hard mask layer within the via area is patterned to form a partial via opened hard mask layer. Simultaneously, the partial via opened hard mask layer within both the trench area and the via area are etched and removed, and the dielectric layer within the via area is partial etched to form a partially opened dielectric layer to: expose a portion of dielectric layer within the trench area; and form a partial via within the partially opened dielectric layer. The partially opened dielectric layer is etched: within the trench area to form a trench; and within the via area to form a final via exposing a portion of etch stop layer. The trench and the final via forming the dual damascene opening.

摘要翻译： 一种用于形成双镶嵌开口的方法，包括以下步骤。 提供了一种其中形成有暴露的导电结构的结构。 在结构和暴露的导电结构之上形成蚀刻停止层。 在蚀刻停止层上方形成介电层。 在电介质层上形成硬掩模层。 图案化硬掩模层以形成部分打开的硬掩模层。 部分打开的硬掩模层具有沟槽区域和通孔区域。 将通孔区域内的部分打开的硬掩模层图案化以形成部分通孔打开的硬掩模层。 同时蚀刻去除在沟槽区域和通孔区域内的部分通孔打开的硬掩模层，并且将通孔区域内的电介质层部分地蚀刻以形成部分打开的电介质层，以使其内部的介电层的一部分露出 沟渠区域; 并且在部分打开的电介质层内形成部分通孔。 蚀刻部分开放的电介质层：在沟槽区域内形成沟槽; 并且在通孔区域内，通过暴露一部分蚀刻停止层形成最终的通孔。 沟槽和最后通孔形成双镶嵌开口。

公开(公告)号：US06720256B1

公开(公告)日：2004-04-13

申请号：US10309428

申请日：2002-12-04

申请人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： An improved method of patterning photoresist during formation of damascene structures is provided which involves a process that is resistant to poisoning from adjacent layers. An inert resin is used to fill vias in a damascene stack. Then a second stack comprised of an underlayer, a non-photosensitive Si-containing layer, an ARC, and a photoresist are formed on the first stack. A trench pattern formed in the photoresist is etch transferred into the first stack. The Si-containing layer that is preferably a spin-on material can be optimized for thermal and etch resistance without compromising lithographic properties since it is not photosensitive. The state of the art photoresist provides a large process window for printing small features with no scum. The inert resin, underlayer, and silicon containing layers are independent of exposure wavelength and can be readily implemented into existing or future manufacturing schemes.

摘要翻译： 提供了一种在形成镶嵌结构期间图案化光刻胶的改进方法，该方法涉及耐相邻层中毒的方法。 使用惰性树脂填充镶嵌叠层中的通孔。 然后在第一叠层上形成由底层，非感光性含硅层，ARC和光致抗蚀剂构成的第二叠层。 在光致抗蚀剂中形成的沟槽图案被蚀刻转移到第一堆叠中。 优选为旋涂材料的含Si层可以针对耐热和耐蚀刻性而优化，而不损害光刻性能，因为它不是光敏的。 最先进的光致抗蚀剂提供了用于打印没有浮渣的小特征的大的工艺窗口。 惰性树脂，底层和含硅层独立于曝光波长，并且可以容易地实现到现有或将来的制造方案中。

公开(公告)号：US06551938B1

公开(公告)日：2003-04-22

申请号：US10056979

申请日：2002-01-25

申请人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L21311

CPC分类号： H01L21/0332 ,  G03F7/075 ,  G03F7/095 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31138

摘要： A method of bi-layer top surface imaging, comprising the following steps. A structure having a lower layer formed thereover is provided. An upper silicon-containing photoresist layer is formed upon the lower layer. The upper silicon-containing photoresist layer is selectively exposed to form upper silicon-containing photoresist layer exposed portions. The upper silicon-containing photoresist layer exposed portions and the portions of the lower layer below the upper silicon-containing photoresist layer exposed portions are removed using an O2-free N2/H2 plasma etch.

摘要翻译： 一种双层顶面成像方法，包括以下步骤。 提供了一种其上形成有下层的结构。 上层含硅光致抗蚀剂层形成在下层。 选择性地暴露上部含硅光致抗蚀剂层以形成上部含硅光致抗蚀剂层暴露部分。 使用无O2的N 2 / H 2等离子体蚀刻去除上部含硅光致抗蚀剂层暴露部分和下部上部含硅光致抗蚀剂层暴露部分下方的部分。

公开(公告)号：US06376366B1

公开(公告)日：2002-04-23

申请号：US09860371

申请日：2001-05-21

申请人： Li-Te S. Lin ,  Li-Chih Chao

发明人： Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76813 ,  Y10S438/942

摘要： A method is provided for forming dual damascene structures with a partial hard mask through a judicious use of partial opening or etching of the mask which simplifies the dual damascene process, and makes it especially suitable for low-k dielectric materials in advanced sub-micron technologies capable of forming features approaching less than 0.10 micrometers (&mgr;m). This is accomplished by forming a hard mask over a low-k dielectric layer. The hard mask is first opened partially to form a trench, and later again to form a via opening. The via opening is next extended into the low-k dielectric layer, followed by etching further the partial trench into the hard mask, and then transferring the trench pattern into the dielectric layer while at the same time extending the via opening to the underlying metal layer.

摘要翻译： 提供了通过明智地使用掩模的部分打开或蚀刻来形成具有部分硬掩模的双镶嵌结构的方法，其简化了双镶嵌工艺，并且使其特别适用于先进亚微米技术中的低k电介质材料 能够形成接近小于0.10微米（mum）的特征。 这是通过在低k电介质层上形成硬掩模来实现的。 首先将硬掩模部分地打开以形成沟槽，然后再次形成通孔。 通孔开口接下来延伸到低k电介质层中，随后将部分沟槽进一步蚀刻到硬掩模中，然后将沟槽图案转移到电介质层中，同时将通孔开口延伸到下面的金属层 。

公开(公告)号：US6063711A

公开(公告)日：2000-05-16

申请号：US69456

申请日：1998-04-28

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

IPC分类号： H01L21/768 ,  H01L21/304 ,  B24B1/00 ,  H01L21/461

CPC分类号： H01L21/7681 ,  H01L21/76807

摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.

摘要翻译： 公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。 由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。 因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

公开(公告)号：US06458650B1

公开(公告)日：2002-10-01

申请号：US09908821

申请日：2001-07-20

申请人： Yi-Chen Huang ,  Li-Chih Chao ,  Chao-Chen Chen

发明人： Yi-Chen Huang ,  Li-Chih Chao ,  Chao-Chen Chen

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/76814

摘要： A new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO2) Glass (FSG) . A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO2) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer-of insulation and exposing the surface of the layer of insulation. Next-and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.

摘要翻译： 提供了一种新的方法，用于创建MIM电容器的第二电极将要沉积的开口。 MIM的第一电极在氟掺杂二氧化硅（SiO 2）玻璃（FSG）的第一层中产生。 包含氮化硅的绝缘层沉积在第一电极的表面上。 氟化二氧化硅（SiO 2）玻璃（FSG）的第二层沉积在氮化硅层的表面上，氮化硅的蚀刻停止层沉积在第二层FSG的表面上。 蚀刻停止层和FSG的第二层被图案化和蚀刻使用干蚀刻，停止在绝缘层上并暴露绝缘层的表面。 接下来对于本发明至关重要的是对氮化硅层的表面的光致抗蚀剂灰化和氧化的步骤。 现在可以同时去除光致抗蚀剂层，使用湿条，从氮化硅层的表面去除氮化硅层的氧化层。 然后可以通过产生MIM电容器的第二电极来进行制造MIM电容器的过程。

公开(公告)号：US06323121B1

公开(公告)日：2001-11-27

申请号：US09570018

申请日：2000-05-12

申请人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

发明人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

摘要： A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

摘要翻译： 描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。 该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。 该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。 该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤 ，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

公开(公告)号：US06743732B1

公开(公告)日：2004-06-01

申请号：US09769812

申请日：2001-01-26

申请人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

发明人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76813

摘要： A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast. The invention's NH3 only etch had a 30 to 80% high etch rate than N2/H2 etches of low-k materials like Silk™.

摘要翻译： 仅使用NH3或NH3 / H2或NH3 / H2气体的有机低k电介质层的等离子体蚀刻工艺。 在衬底上形成低k电介质层。 在低k电介质层上形成掩模图案。 掩模图案具有开口。 使用本发明的蚀刻工艺，使用掩模图案作为蚀刻掩模，通过开口蚀刻低k电介质层。 在第一实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3气体来蚀刻低k电介质层。 在第二实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / H 2气体来蚀刻低k电介质层。 在第三实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / N 2气体来蚀刻低k电介质层。 本发明的含NH 3的等离子体蚀刻意外地快速蚀刻有机低k材料。 本发明的仅NH3蚀刻具有比Silk TM的低k材料的N 2 / H 2蚀刻高30至80％的高蚀刻速率。

公开(公告)号：US06727183B1

公开(公告)日：2004-04-27

申请号：US09915842

申请日：2001-07-27

申请人： Ching-Hui Ma ,  Jen-Cheng Liu ,  Li-Chih Chao

发明人： Ching-Hui Ma ,  Jen-Cheng Liu ,  Li-Chih Chao

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/31116 ,  H01L21/76807

摘要： A novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is described. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种用于防止镶嵌金属化中的超低k材料层的尖锐和底切的新颖蚀刻方法。 待接触的区域设置在半导体衬底中或其上。 衬垫层被覆盖在待接触的区域上。 沉积在衬层上的超低k电介质层。 通过超低k电介质层将镶嵌开口蚀刻到覆盖待接触区域的衬垫层，其中该蚀刻包括高F / C比蚀刻化学，高功率和低压。 镶嵌开口内的衬里层被蚀刻掉以暴露待接触的区域，其中该蚀刻包括高F / C比蚀刻化学，低功率和低压，以在集成电路的制造中完成镶嵌开口的形成 设备。