公开(公告)号：US6100119A

公开(公告)日：2000-08-08

申请号：US57538

申请日：1998-04-09

Applicant: Jin Jang ,  Kyung-Ha Lee ,  You-Chan Chung

Inventor： Jin Jang ,  Kyung-Ha Lee ,  You-Chan Chung

IPC: H01L29/49 ,  H01L21/336 ,  H01L21/84

CPC classification number: H01L29/4908

Abstract: A thin film transistor includes an insulating substrate; a polysilicon pattern formed on the insulating substrate; a first nitride layer disposed on a channel portion of the polysilicon pattern; heavily doped semiconductor layer regions disposed in upper portions of the polysilicon pattern on sides of the first nitride layer pattern; an interlevel insulating layer disposed on the insulating substrate, the polysilicon pattern, the first nitride layer and the heavily doped semiconductor layer regions, the interlevel insulating layer having a contact hole to expose a portion of the heavily doped semiconductor layer; source and drain electrodes connected to the heavily doped semiconductor layer regions through the contact hole; and a gate electrode formed on the interlevel insulating layer disposed on the first nitride layer.

Abstract translation: 薄膜晶体管包括绝缘基板; 形成在所述绝缘基板上的多晶硅图案; 设置在所述多晶硅图案的沟道部分上的第一氮化物层; 在第一氮化物层图案的侧面上设置在多晶硅图案的上部的重掺杂半导体层区域; 设置在所述绝缘基板上的层间绝缘层，所述多晶硅图案，所述第一氮化物层和所述重掺杂半导体层区域，所述层间绝缘层具有用于暴露所述重掺杂半导体层的一部分的接触孔; 源极和漏极通过接触孔连接到重掺杂半导体层区域; 以及形成在设置在第一氮化物层上的层间绝缘层上的栅电极。

公开(公告)号：US6037611A

公开(公告)日：2000-03-14

申请号：US980311

申请日：1997-11-28

Applicant: Jin Jang ,  Kyung-Ha Lee

Inventor： Jin Jang ,  Kyung-Ha Lee

IPC: H01L27/12 ,  H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A method of fabricating a thin film transistor includes the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the metal layer; etching the metal layer and the insulating layer by using the photoresist pattern as a mask, and respectively forming a gate electrode and a gate insulating layer to expose a part of the active layer; forming an amorphous silicon layer on the resultant whole surface of the substrate; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer and a source/drain electrode; and carrying out a lift-off process to remove the photoresist pattern, and exposing the surface on the gate electrode.

Abstract translation: 制造薄膜晶体管的方法包括在绝缘基板上形成有源层的步骤; 在所述有源层上形成绝缘层和第一金属层; 形成用于在所述金属层上形成栅电极的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为掩模蚀刻金属层和绝缘层，并分别形成栅极电极和栅极绝缘层以暴露活性层的一部分; 在所得基板的整个表面上形成非晶硅层; 在所述非晶硅层上形成第二金属层; 通过光刻工艺图案化第二金属层和非晶硅层以形成偏移层和源极/漏极; 并进行剥离处理以除去光致抗蚀剂图案，并使栅电极上的表面露出。

公开(公告)号：US06316295B1

公开(公告)日：2001-11-13

申请号：US09407114

申请日：1999-09-27

Applicant: Jin Jang ,  Kyung-Ha Lee

Inventor： Jin Jang ,  Kyung-Ha Lee

IPC: H01L2100

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A method of fabricating a thin film transistor includes the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the metal layer; etching the metal layer and the insulating layer by using the photoresist pattern as a mask, and respectively forming a gate electrode and a gate insulating layer to expose a part of the active layer; forming an amorphous silicon layer on the resultant whole surface substrate; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer and a source/drain electrode; and carrying out a lift-off process to remove the photoresist pattern, and exposing the surface on the gate electrode.

Abstract translation: 制造薄膜晶体管的方法包括在绝缘基板上形成有源层的步骤; 在所述有源层上形成绝缘层和第一金属层; 形成用于在所述金属层上形成栅电极的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为掩模蚀刻金属层和绝缘层，并分别形成栅极电极和栅极绝缘层以暴露活性层的一部分; 在所得整个表面基板上形成非晶硅层; 在所述非晶硅层上形成第二金属层; 通过光刻工艺图案化第二金属层和非晶硅层以形成偏移层和源极/漏极; 并进行剥离处理以除去光致抗蚀剂图案，并使栅电极上的表面露出。

公开(公告)号：US5783852A

公开(公告)日：1998-07-21

申请号：US697839

申请日：1996-08-30

Applicant: Jin Jang ,  Kyung-Ha Lee ,  You-Chan Chung

Inventor： Jin Jang ,  Kyung-Ha Lee ,  You-Chan Chung

IPC: H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/4908

Abstract: A thin film transistor includes an insulating substrate; a polysilicon pattern formed on the insulating substrate; a first nitride layer disposed on a channel portion of the polysilicon pattern; heavily doped semiconductor layer regions disposed in upper portions of the polysilicon pattern on sides of the first nitride layer pattern; an interlevel insulating layer disposed on the insulating substrate, the polysilicon pattern, the first nitride layer and the heavily doped semiconductor layer regions, the interlevel insulating layer having a contact hole to expose a portion of the heavily doped semiconductor layer; source and drain electrodes connected to the heavily doped semiconductor layer regions through the contact hole; and a gate electrode formed on the interlevel insulating layer disposed on the first nitride layer.

公开(公告)号：US07688370B2

公开(公告)日：2010-03-30

申请号：US11295373

申请日：2005-12-06

Applicant: Ji-Ho Hur ,  Se-Hwan Kim ,  Jin Jang

Inventor： Ji-Ho Hur ,  Se-Hwan Kim ,  Jin Jang

IPC: H04N3/14

CPC classification number: H04N5/37452 ,  H04N5/3559

Abstract: Disclosed is an active pixel sensor array, which can reduce the number of elements and the size of capacitors by enabling a reset switching transistor to include a function of an optical sensor and to reset a pixel voltage with a power supply voltage VDD after a gate selection signal is outputted, and to reset a pixel voltage with a power supply voltage VDD by a coupling function in case that a gate selection signal is outputted. The active pixel image sensor having a gate driving circuit and a column driving circuit includes a pixel composed of a voltage supply unit for supplying a signal voltage to the column driving circuit; a gate selection unit for turning on according to a n+1-th gate selection signal and outputting a voltage based on a difference between a pixel voltage and a threshold voltage of the voltage supply unit; a reset switching unit for turning on according to a n+1-th gate selection signal and resetting the pixel voltage with a power supply voltage VDD; and a storage unit and a coupling unit for coupling so as to initialize the pixel voltage to be lower than the power supply voltage VDD just after the n+1-th gate selection signal is outputted.

Abstract translation: 公开了一种有源像素传感器阵列，其可以通过使复位开关晶体管包括光学传感器的功能并且在栅极选择之后以电源电压VDD复位像素电压来减少元件的数量和电容器的尺寸 在输出栅极选择信号的情况下，通过耦合功能输出信号，并且利用电源电压VDD复位像素电压。 具有栅极驱动电路和列驱动电路的有源像素图像传感器包括由用于向列驱动电路提供信号电压的电压供给单元构成的像素; 栅极选择单元，用于根据第n + 1栅极选择信号导通，并且基于像素电压和电压提供单元的阈值电压之间的差输出电压; 复位开关单元，用于根据第n + 1个选通信号导通，并用电源电压VDD复位像素电压; 以及存储单元和耦合单元，用于耦合以将像素电压初始化为低于在输出第n + 1门选通信号之后的电源电压VDD。

公开(公告)号：US07662681B2

公开(公告)日：2010-02-16

申请号：US11609374

申请日：2006-12-12

Applicant: Jin Jang ,  Jun-Hyuk Cheon

Inventor： Jin Jang ,  Jun-Hyuk Cheon

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/78678 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66765

Abstract: Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer.

Abstract translation: 本文公开了一种用于制造反向交错多晶硅薄膜晶体管的方法，更具体地说，一种用于制造反向交错多晶硅薄膜晶体管的方法，其中磷硅酸盐旋涂玻璃（P-SOG）用于 栅极绝缘膜。 该方法包括以下步骤：在绝缘基板上形成缓冲层; 在缓冲层上形成栅极金属图案; 在栅极金属图案上形成平坦化的栅极绝缘膜; 在栅极绝缘膜上沉积非晶硅层; 将所述非晶硅层结晶成多晶硅层; 在多晶硅层上形成n +或p +层; 在n +或p +层上形成源极/漏极金属层; 以及在源极/漏极金属层上形成钝化层。

公开(公告)号：US20090032873A1

公开(公告)日：2009-02-05

申请号：US11895125

申请日：2007-08-23

Applicant: Jeffrey Scott Cites ,  Jin Jang ,  ChuanChe Wang ,  Carlo Anthony Kosik Williams ,  Sung Eun Ahn

Inventor： Jeffrey Scott Cites ,  Jin Jang ,  ChuanChe Wang ,  Carlo Anthony Kosik Williams ,  Sung Eun Ahn

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L21/2007 ,  H01L29/78654

Abstract: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor single crystal semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing a cleaved surface of the exfoliation layer; subjecting the cleaved surface of the exfoliation layer to a dry etching process to produce a single crystal semiconductor layer of about 5-20 nm thickness; and forming a thin film transistor in the thin semiconductor layer.

Abstract translation: 用于制造玻璃（SiOG）结构的半导体的方法和装置包括：使施主单晶半导体晶片的注入表面进行离子注入工艺以产生施主半导体晶片的剥离层; 使用电解将剥离层的注入表面粘合到玻璃基板上; 将剥离层与施主半导体晶片分离，从而暴露剥离层的切割表面; 使剥离层的切割表面进行干蚀刻工艺以产生约5-20nm厚度的单晶半导体层; 以及在所述薄半导体层中形成薄膜晶体管。

公开(公告)号：US20090021287A1

公开(公告)日：2009-01-22

申请号：US11662605

申请日：2004-09-15

Applicant: Jin Jang ,  Joon-Chul Goh

Inventor： Jin Jang ,  Joon-Chul Goh

IPC: H03K3/00

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2320/043

Abstract: A drive circuit for organic light emitting diodes (OLEDs), and a method for driving OLEDs, using the drive circuit. The drive circuit includes pixel circuits, each of which includes a first transistor for receiving a data voltage, and outputting a drive current to an OLED, a second transistor for transmitting the data voltage to the first transistor, a third transistor for connecting the gate and drain of the first transistor, a capacitor for storing a gate voltage of the first transistor, and a fourth transistor connected to the drain of the first transistor. The OLED is connected to the source of the first transistor by a fifth transistor, or is directly connected to the source of the first transistor without using the fifth transistor. The drive circuit generates drive current, based on a non-uniformity-compensated threshold voltage of the first transistor, thereby obtaining a uniform luminance of the OLED.

Abstract translation: 用于有机发光二极管（OLED）的驱动电路，以及使用驱动电路驱动OLED的方法。 驱动电路包括像素电路，每个像素电路包括用于接收数据电压的第一晶体管和向OLED输出驱动电流，用于将数据电压传输到第一晶体管的第二晶体管，用于连接栅极和 第一晶体管的漏极，用于存储第一晶体管的栅极电压的电容器和连接到第一晶体管的漏极的第四晶体管。 OLED通过第五晶体管连接到第一晶体管的源极，或者直接连接到第一晶体管的源极而不使用第五晶体管。 驱动电路基于第一晶体管的不均匀补偿阈值电压产生驱动电流，从而获得OLED的均匀亮度。

公开(公告)号：US20070069637A1

公开(公告)日：2007-03-29

申请号：US11321703

申请日：2005-12-29

Applicant: Jin Jang ,  Yong-Kyun Lee

Inventor： Jin Jang ,  Yong-Kyun Lee

IPC: H05B33/00 ,  H01J1/62

CPC classification number: H01L51/50 ,  B82Y30/00 ,  H01L51/5088

Abstract: A polymer light emitting diode having an interinsulation layer between a hole injecting layer (or a hole transporting layer) and a light emitting polymer layer, and a method for fabricating the polymer light emitting diode. The polymer light emitting diode having the interinsulation layer includes a hole injecting layer formed on an anode layer, formed on a glass substrate, by coating or printing; the interinsulation layer having a designated thickness formed on the hole injecting layer; a light emitting polymer layer formed on the interinsulation layer by coating or printing; and an electron injecting layer formed on the light emitting polymer layer, and a cathode layer formed on the electron injecting layer.

Abstract translation: 具有空穴注入层（或空穴传输层）和发光聚合物层之间的绝缘层的聚合物发光二极管及其制造方法。 具有绝缘层的聚合物发光二极管包括通过涂布或印刷形成在玻璃基板上的阳极层上形成的空穴注入层; 所述绝缘层具有形成在所述空穴注入层上的指定厚度; 通过涂布或印刷在绝缘层上形成的发光聚合物层; 以及形成在发光聚合物层上的电子注入层和形成在电子注入层上的阴极层。

公开(公告)号：US20060286780A1

公开(公告)日：2006-12-21

申请号：US10570285

申请日：2004-09-02

Applicant: Jin Jang ,  Jong-Hyun Choi ,  Seung-Soo Kim ,  Jae-Hwan Oh ,  Jun-Hyuk Chon

Inventor： Jin Jang ,  Jong-Hyun Choi ,  Seung-Soo Kim ,  Jae-Hwan Oh ,  Jun-Hyuk Chon

IPC: H01L21/20

CPC classification number: H01L21/02532 ,  H01L21/02425 ,  H01L21/02488 ,  H01L21/02672 ,  H01L27/1277 ,  H01L29/78603

Abstract: Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film (120) formed on the metal substrate (110). An amorphous silicon layer (130) is formed on the insulation film (120). A metal layer (140) is formed on the amorphous silicon layer (130). A sample on the metal substrate (110) is heated and crystallized.

Abstract translation: 公开了一种在基板上形成硅薄膜的方法，更具体地说，涉及一种在柔性金属基板上形成质量好的多晶硅薄膜的方法。 准备金属基板（110），使金属基板（110）的表面变平。 形成在金属基板（110）上的绝缘膜（120）。 在绝缘膜（120）上形成非晶硅层（130）。 金属层（140）形成在非晶硅层（130）上。 将金属基板（110）上的样品加热并结晶。