公开(公告)号：US08249847B2

公开(公告)日：2012-08-21

申请号：US12045137

申请日：2008-03-10

申请人： Jin Zhu ,  Ming Wang ,  Chih-Yi Tu

发明人： Jin Zhu ,  Ming Wang ,  Chih-Yi Tu

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  H05K13/085

摘要： An exemplary simulation system for manufacturing a printed circuit board is provided. The simulation system includes at least one simulation sub-system. The simulation sub-system includes an input module, a storing module, a processing module, and an output module. The input module is configured for acquiring a number of processing parameters associated with steps of a process for manufacturing the printed circuit board. The storing module is configured for storing a number of simulation functions relating to the steps of the process for manufacturing the printed circuit board. The processing module is configured for selecting and performing the corresponding simulation function according to the acquired parameters, thereby obtaining a simulation result. The output module is configured for output the simulation result.

摘要翻译： 提供了用于制造印刷电路板的示例性模拟系统。 仿真系统包括至少一个仿真子系统。 仿真子系统包括输入模块，存储模块，处理模块和输出模块。 输入模块被配置为用于获取与用于制造印刷电路板的工艺的步骤相关联的多个处理参数。 存储模块被配置为存储与制造印刷电路板的工艺步骤相关的多个模拟功能。 处理模块被配置为根据获取的参数来选择和执行相应的模拟功能，从而获得模拟结果。 输出模块配置为输出仿真结果。

公开(公告)号：US20090088881A1

公开(公告)日：2009-04-02

申请号：US12045137

申请日：2008-03-10

申请人： Jin Zhu ,  Ming Wang ,  Chih-Yi Tu

发明人： Jin Zhu ,  Ming Wang ,  Chih-Yi Tu

IPC分类号： G06F17/00

CPC分类号： G06F17/5009 ,  H05K13/085

摘要： An exemplary simulation system for manufacturing a printed circuit board is provided. The simulation system includes at least one simulation sub-system. The simulation sub-system includes an input module, a storing module, a processing module, and an output module. The input module is configured for acquiring a number of processing parameters associated with steps of a process for manufacturing the printed circuit board. The storing module is configured for storing a number of simulation functions relating to the steps of the process for manufacturing the printed circuit board. The processing module is configured for selecting and performing the corresponding simulation function according to the acquired parameters, thereby obtaining a simulation result. The output module is configured for output the simulation result.

摘要翻译： 提供了用于制造印刷电路板的示例性模拟系统。 仿真系统包括至少一个仿真子系统。 仿真子系统包括输入模块，存储模块，处理模块和输出模块。 输入模块被配置为用于获取与用于制造印刷电路板的工艺的步骤相关联的多个处理参数。 存储模块被配置为存储与制造印刷电路板的工艺步骤相关的多个模拟功能。 处理模块被配置为根据获取的参数来选择和执行相应的模拟功能，从而获得模拟结果。 输出模块配置为输出仿真结果。

公开(公告)号：US08049113B2

公开(公告)日：2011-11-01

申请号：US12047152

申请日：2008-03-12

申请人： Dong-Qing He ,  Ming Wang ,  Chih-Yi Tu ,  Cheng-Hsien Lin

发明人： Dong-Qing He ,  Ming Wang ,  Chih-Yi Tu ,  Cheng-Hsien Lin

IPC分类号： H05K1/02

CPC分类号： H05K1/025 ,  H05K1/111 ,  H05K2201/09727 ,  Y02P70/611

摘要： The present invention relates to a printed circuit board. In one embodiment, a printed circuit board includes a dielectric layer and a conductive trace formed on the dielectric layer. The conductive layer includes a first conductive portion, a connecting portion and a second conductive portion. The connecting portion includes a first end and a second end. The first end is connected to the first conductive portion; the second end is connected to the second conductive portion. A width of the connecting portion gradually decreases from the first end to the second end. Reflection and cross talk of signals transmitted in the presented printed circuit board can be reduced.

摘要翻译： 印刷电路板技术领域本发明涉及印刷电路板。 在一个实施例中，印刷电路板包括介电层和形成在电介质层上的导电迹线。 导电层包括第一导电部分，连接部分和第二导电部分。 连接部分包括第一端和第二端。 第一端连接到第一导电部分; 第二端连接到第二导电部分。 连接部的宽度从第一端到第二端逐渐减小。 可以减少在所呈现的印刷电路板中传输的信号的反射和串扰。

公开(公告)号：US07581312B2

公开(公告)日：2009-09-01

申请号：US11877585

申请日：2007-10-23

申请人： Chih-Yi Tu ,  Cheng-Hsien Lin ,  Ming Wang

发明人： Chih-Yi Tu ,  Cheng-Hsien Lin ,  Ming Wang

IPC分类号： H05K3/20

CPC分类号： H05K3/4697 ,  H05K1/0393 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method for manufacturing a multilayer FPCB includes the steps of: providing a first copper clad laminate, a second copper clad laminate and a binder layer; defining an opening on the binder layer; defining a first slit on the first copper clad laminate; laminating the first copper clad laminate, the binder layer and the second copper clad laminate; defining a via hole for establishing electric connection between the first copper clad laminate and the second copper clad laminate; cutting the first copper clad laminate, the binder layer and the second copper clad laminate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.

摘要翻译： 制造多层FPCB的方法包括以下步骤：提供第一覆铜层压板，第二覆铜层压板和粘合剂层; 在粘合剂层上限定开口; 在所述第一覆铜层压板上限定第一狭缝; 层压第一覆铜层压板，粘合剂层和第二覆铜层压板; 限定用于在所述第一覆铜层压板和所述第二覆铜层压板之间建立电连接的通孔; 切割第一覆铜层压板，粘合剂层和第二覆铜层压板，从而形成在不同区域中具有不同层数的多层柔性印刷电路板。

公开(公告)号：US20080283289A1

公开(公告)日：2008-11-20

申请号：US12047152

申请日：2008-03-12

申请人： Dong-Qing He ,  Ming Wang ,  Chih-Yi Tu ,  Cheng-Hsien Lin

发明人： Dong-Qing He ,  Ming Wang ,  Chih-Yi Tu ,  Cheng-Hsien Lin

IPC分类号： H05K1/02

CPC分类号： H05K1/025 ,  H05K1/111 ,  H05K2201/09727 ,  Y02P70/611

摘要： The present invention relates to a printed circuit board. In one embodiment, a printed circuit board includes a dielectric layer and a conductive trace formed on the dielectric layer. The conductive layer includes a first conductive portion, a connecting portion and a second conductive portion. The connecting portion includes a first end and a second end. The first end is connected to the first conductive portion; the second end is connected to the second conductive portion. A width of the connecting portion gradually decreases from the first end to the second end. Reflection and cross talk of signals transmitted in the presented printed circuit board can be reduced.

摘要翻译： 印刷电路板技术领域本发明涉及印刷电路板。 在一个实施例中，印刷电路板包括介电层和形成在电介质层上的导电迹线。 导电层包括第一导电部分，连接部分和第二导电部分。 连接部分包括第一端和第二端。 第一端连接到第一导电部分; 第二端连接到第二导电部分。 连接部的宽度从第一端到第二端逐渐减小。 可以减少在所呈现的印刷电路板中传输的信号的反射和串扰。

公开(公告)号：US20090039895A1

公开(公告)日：2009-02-12

申请号：US12143632

申请日：2008-06-20

申请人： Li Xiao ,  I-Hsien Chiang ,  Chih-Yi Tu

发明人： Li Xiao ,  I-Hsien Chiang ,  Chih-Yi Tu

IPC分类号： G01R31/04

CPC分类号： G01R31/2812

摘要： A method of detecting faulty via holes of a printed circuit board. The printed circuit board including a number of electric trace segments. The method includes steps of: providing a testing system, the testing system comprising a processor, a storing means and a resistance measuring device, the storing means for storing a function Ymin=fmin(X) wherein X represents a reference resistance associated with a given electric trace segment, Ymin represents a minimum threshold value; measuring a resistance of an electric trace segment of a to-be-tested printed circuit board using the resistance measuring device, a to-be-tested via hole located on the electric trace segment; and judging whether the to-be-tested via hole is a faulty via hole according to the following criteria: if |Xa−X|≧Ymin, the to-be-tested via hole is a faulty via hole, and if |Xa−X|

摘要翻译： 一种检测印刷电路板故障通孔的方法。 印刷电路板包括多个电迹线段。 该方法包括以下步骤：提供测试系统，所述测试系统包括处理器，存储装置和电阻测量装置，所述存储装置用于存储功能Ymin = fmin（X），其中X表示与给定的相关联的参考电阻 电迹线段，Ymin表示最小阈值; 使用电阻测量装置测量待测试印刷电路板的电迹线段的电阻，该电阻测量装置是位于电迹线段上的待测试通孔; 并且根据以下标准判断被测试的通孔是否是故障的通孔：如果| Xa-X |> = Ymin，待测试的通孔是故障的通孔，如果| Xa -X |

公开(公告)号：US08453321B2

公开(公告)日：2013-06-04

申请号：US13164776

申请日：2011-06-21

申请人： Jun-Qing Zhang ,  Chih-Yi Tu ,  Szu-Min Huang

发明人： Jun-Qing Zhang ,  Chih-Yi Tu ,  Szu-Min Huang

IPC分类号： H05K3/46

CPC分类号： H05K3/4697 ,  H05K1/0393 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0394 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2203/061 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method for manufacturing a multilayer FPCB which includes providing a first substrate, a second substrate and a binder layer; defining an opening on the binder layer; defining a first slit in the dielectric layer of the first substrate; laminating the first substrate, the binder layer and the second substrate; forming a second slit in the conductive layer of the first substrate, the second slit being created so as to align with the first slit, cutting the first substrate, the binder layer and the second substrate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.

摘要翻译： 一种制造多层FPCB的方法，包括提供第一基板，第二基板和粘合剂层; 在粘合剂层上限定开口; 限定所述第一基板的介电层中的第一狭缝; 层压第一基板，粘合剂层和第二基板; 在所述第一基板的所述导电层中形成第二狭缝，所述第二狭缝被形成为与所述第一狭缝对准，切割所述第一基板，所述粘合剂层和所述第二基板，从而形成具有不同数量的多层柔性印刷电路板 的层次在不同的地区。

公开(公告)号：US07897055B2

公开(公告)日：2011-03-01

申请号：US11865619

申请日：2007-10-01

申请人： Chih-Yi Tu ,  Cheng-Hsien Lin ,  I-Hsien Chiang

发明人： Chih-Yi Tu ,  Cheng-Hsien Lin ,  I-Hsien Chiang

IPC分类号： H01B13/00 ,  B44C1/22 ,  C23F1/00

CPC分类号： H05K3/4697 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/429 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2203/063 ,  H05K2203/108 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

摘要： The present inventions relates to a method for manufacturing a multilayer FPCB having different number of layers in different areas. The method includes the steps of: providing a binder layer; removing a portion of the binder layer thereby defining an opening in the binder layer; forming a multilayer FPCB which having a first copper clad laminate structure and a second copper clad laminate structure disposed on two opposite sides of the binder layer respectively using the binder layer; cutting the first copper clad laminate structure; cutting the multilayer FPCB in manner that a portion of first copper clad laminate structure that is exposed to the opening is separated from the first copper clad structure thereby obtain a multilayer FPCB having different number of layers in different areas.

摘要翻译： 本发明涉及一种制造在不同区域中具有不同层数的多层FPCB的方法。 该方法包括以下步骤：提供粘合剂层; 去除粘合剂层的一部分从而限定粘合剂层中的开口; 形成具有第一覆铜层压结构的多层FPCB和分别使用粘合剂层设置在粘合剂层的两个相对侧上的第二覆铜层压结构; 切割第一个覆铜层压结构; 以暴露于开口的第一覆铜层压体结构的一部分与第一铜包层结构体分离的方式切断多层FPCB，由此得到在不同区域中具有不同层数的多层FPCB。

公开(公告)号：US08049511B2

公开(公告)日：2011-11-01

申请号：US12143632

申请日：2008-06-20

申请人： Li Xiao ,  I-Hsien Chiang ,  Chih-Yi Tu

发明人： Li Xiao ,  I-Hsien Chiang ,  Chih-Yi Tu

IPC分类号： G01R31/08

CPC分类号： G01R31/2812

摘要： A method of detecting faulty via holes of a printed circuit board. The printed circuit board including a number of electric trace segments. The method includes steps of: providing a testing system, the testing system comprising a processor, a storing means and a resistance measuring device, the storing means for storing a function Ymin=fmin(X) wherein X represents a reference resistance associated with a given electric trace segment, Ymin represents a minimum threshold value; measuring a resistance of an electric trace segment of a to-be-tested printed circuit board using the resistance measuring device, a to-be-tested via hole located on the electric trace segment; and judging whether the to-be-tested via hole is a faulty via hole according to the following criteria: if |Xa−X|≧Ymin, the to-be-tested via hole is a faulty via hole, and if |Xa−X|

摘要翻译： 一种检测印刷电路板故障通孔的方法。 印刷电路板包括多个电迹线段。 该方法包括以下步骤：提供测试系统，所述测试系统包括处理器，存储装置和电阻测量装置，所述存储装置用于存储功能Ymin = fmin（X），其中X表示与给定的相关联的参考电阻 电迹线段，Ymin表示最小阈值; 使用电阻测量装置测量待测试印刷电路板的电迹线段的电阻，该电阻测量装置是位于电迹线段上的待测试通孔; 并且根据以下标准判断被测试的通孔是否是故障的通孔：如果| Xa-X |≥Ymin，待测试的通孔是故障的通孔，并且如果| Xa- X |

公开(公告)号：US08042265B2

公开(公告)日：2011-10-25

申请号：US11957324

申请日：2007-12-14

申请人： Jun-Qing Zhang ,  Chih-Yi Tu ,  Szu-Min Huang

发明人： Jun-Qing Zhang ,  Chih-Yi Tu ,  Szu-Min Huang

IPC分类号： H05K3/46

CPC分类号： H05K3/4697 ,  H05K1/0393 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0394 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2203/061 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method for manufacturing a multilayer FPCB includes the steps of: providing a first substrate, a second substrate and a binder layer; defining an opening on the binder layer; defining a first slit in the dielectric layer of the first substrate; laminating the first substrate, the binder layer and the second substrate; forming a second slit in the conductive layer of the first substrate, the second slit is configured to be aligned with the first slit, cutting the first substrate, the binder layer and the second substrate thereby forming a multilayer flexible printed circuit board having different numbers of layers in different areas.

摘要翻译： 一种制造多层FPCB的方法包括以下步骤：提供第一基板，第二基板和粘合剂层; 在粘合剂层上限定开口; 限定所述第一基板的介电层中的第一狭缝; 层压第一基板，粘合剂层和第二基板; 在所述第一基板的导电层中形成第二狭缝，所述第二狭缝被构造成与所述第一狭缝对准，切割所述第一基板，所述粘合剂层和所述第二基板，从而形成具有不同数量的多层柔性印刷电路板 不同领域的层次。