公开(公告)号：US08834597B1

公开(公告)日：2014-09-16

申请号：US13485721

申请日：2012-05-31

Applicant: Jin-Woo Han ,  Meyya Meyyappan

Inventor： Jin-Woo Han ,  Meyya Meyyappan

IPC: C22B15/00 ,  B82Y10/00 ,  H01J1/00 ,  H01J1/304

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J1/3048 ,  H01J9/025 ,  H01J2201/3043 ,  H01J2201/30449

Abstract: A method of fabricating metallic Cu nanowires with lengths up to about 25 μm and diameters in a range 20-100 nm, or greater if desired. Vertically oriented or laterally oriented copper oxide structures (CuO and/or Cu2O) are grown on a Cu substrate. The copper oxide structures are reduced with 99+ percent H or H2, and in this reduction process the lengths decrease (to no more than about 25 μm), the density of surviving nanostructures on a substrate decreases, and the diameters of the surviving nanostructures have a range, of about 20-100 nm. The resulting nanowires are substantially pure Cu and can be oriented laterally (for local or global interconnects) or can be oriented vertically (for standard vertical interconnects).

Abstract translation: 如果需要，制造长度大约25μm，直径在20-100nm范围内的金属Cu纳米线的方法或更高。 垂直取向或侧向取向的氧化铜结构（CuO和/或Cu2O）在Cu衬底上生长。 氧化铜结构以99％以上的H或H 2还原，在该还原过程中，长度减小（不大于约25μm），衬底上存活的纳米结构的密度降低，并且存活的纳米结构的直径 约20-100nm的范围。 所得的纳米线基本上是纯Cu，并且可以横向（用于局部或全局互连）或者可以垂直取向（对于标准垂直互连）。

公开(公告)号：US09230651B2

公开(公告)日：2016-01-05

申请号：US13746523

申请日：2013-01-22

Applicant: Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

Inventor： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC: H01L29/78 ,  H01L29/70 ,  G11C16/04 ,  G11C11/404 ,  H01L27/108 ,  G11C16/10 ,  H01L27/115

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/1023 ,  H01L27/11524 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/7841

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Abstract translation: 半导体存储单元包括被配置为被充电到指示从至少第一和第二状态中选择的存储单元的状态的电平的浮动体区域。 存储单元的第一区域与浮体区域电接触。 存储单元的第二区域与第一区域间隔开并且还与浮体区域电接触。 门位于第一和第二区之间。 背偏置区域被配置为当存储器单元处于第一和第二状态之一时产生冲击电离，并且背偏置区被配置为当存储单元位于另一个状态时不产生碰撞电离 第一和第二州。

公开(公告)号：US20210242189A1

公开(公告)日：2021-08-05

申请号：US17151867

申请日：2021-01-19

Applicant: Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/473 ,  H01L21/768 ,  H01L25/00

Abstract: A 3D device, the first level including first transistors and a first interconnect; a second level with second transistors overlaying the first level; a third level with third transistors overlaying the second level; a plurality of electronic circuit units (ECUs), where each ECU includes a first circuit with a portion of the first transistors, where each of the ECUs includes a second circuit including a portion of the second transistors, where each of the plurality of ECUs includes a third circuit, which includes a portion of the third transistors, where each of the ECUs includes a vertical data bus, where the vertical data bus has between eight pillars and three hundreds pillars, where the vertical data bus provides electrical connections between the first and second circuits, where the third level includes an array of memory cells, and where the second circuit includes a memory control circuit.

公开(公告)号：US20180158912A1

公开(公告)日：2018-06-07

申请号：US15724989

申请日：2016-04-27

Applicant: Jin-woo HAN ,  Yuniarto WIDJAJA ,  Zvi OR-BACH ,  Dinesh MAHESHWARI ,  Zeno Semiconductor, Inc.

Inventor： Jin-Woo Han ,  Yuniarto Widjaja ,  Zvi Or-Bach ,  Dinesh Maheshwari

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  G11C16/10 ,  G11C16/26 ,  H01L27/24 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

公开(公告)号：US20100283666A1

公开(公告)日：2010-11-11

申请号：US12690634

申请日：2010-01-20

Applicant: Dong-Weon Lee ,  Jin-Woo Han ,  Kyu-Ha Song ,  Young-Jin Ryoo

Inventor： Dong-Weon Lee ,  Jin-Woo Han ,  Kyu-Ha Song ,  Young-Jin Ryoo

IPC: G01S13/00

CPC classification number: G01S7/021 ,  G01S3/74

Abstract: Disclosed is a radar signal clustering method using frequency modulation characteristics and combination characteristics of signals including: a first step of assigning pulses of received radar signals to cells consisting of parameters including radio frequency (RF) and angle of arrival (AOA) of the pulses; a second step of calculating a pulse density distribution of each cell using a kernel density estimator; a third step of extracting a corresponding cell as a frequency fixed cluster if the calculated pulse density distribution is greater than a threshold of the frequency fixed cluster; a fourth step of making cell groups by merging remaining cells that are not extracted as the frequency fixed clusters; a fifth step of calculating a pulse density distribution of each cell group by using the kernel density estimator for each cell group; and a sixth step of comparing the calculated pulse density distribution for each cell group with each threshold according to a signal combination type of frequency agile clusters, thus to classify and extract each cell group according to the signal combination type.

Abstract translation: 公开了一种使用频率调制特性和信号的组合特性的雷达信号聚类方法，包括：将接收到的雷达信号的脉冲分配给由包括射频（RF）和到达角（AOA）的参数组成的小区的第一步骤; 使用核密度估计器计算每个单元的脉冲密度分布的第二步骤; 如果计算的脉冲密度分布大于频率固定簇的阈值，则提取相应的小区作为频率固定簇的第三步骤; 通过将未提取的剩余单元合并为频率固定簇来制作单元组的第四步骤; 通过使用每个单元组的核密度估计器来计算每个单元组的脉冲密度分布的第五步骤; 以及第六步骤，根据频率敏捷簇的信号组合类型，将每个单元组的计算脉冲密度分布与每个阈值进行比较，从而根据信号组合类型对每个单元组进行分类和提取。

公开(公告)号：US20100203126A1

公开(公告)日：2010-08-12

申请号：US12668328

申请日：2008-07-11

Applicant: Jong-Woo Park ,  Jin-Woo Han ,  Yae-Young Choi

Inventor： Jong-Woo Park ,  Jin-Woo Han ,  Yae-Young Choi

IPC: A61K9/20 ,  A61K31/341 ,  A61K31/355 ,  A61K31/23 ,  A61K31/7056 ,  A61K31/4406 ,  A61K31/675 ,  A61K31/122 ,  A61K33/30 ,  A61K33/26 ,  A61K33/42 ,  A61K9/28

CPC classification number: A61K9/209 ,  A23L33/15 ,  A23L33/16 ,  A23L33/175 ,  A23V2002/00 ,  A61K9/2027 ,  A61K9/2054 ,  A61K31/07 ,  A61K31/12 ,  A61K31/14 ,  A61K31/355 ,  A61K31/375 ,  A61K31/4188 ,  A61K31/44 ,  A61K31/51 ,  A61K31/525 ,  A61K33/26 ,  A61K33/30 ,  A61K33/42 ,  A61K2300/00 ,  A23V2250/314 ,  A23V2250/06 ,  A23V2250/70

Abstract: The present invention relates to a multi-layered vitamin/mineral complex tablet having enhanced stability of ubidecarenone. The present invention is characterized in that ubidecarenone is contained in a first layer, and ingredients decreasing the stability of ubidecarenone are contained in an additional layer separated from the first layer. The method is a convenient process, and the formulation prepared by the method can maintain a high content of ubidecarenone during long-term storage, thereby providing a simultaneous intake of ubidecarenone and nutritional ingredients such as various vitamins.

Abstract translation: 本发明涉及一种具有增强ubidecarenone稳定性的多层维生素/矿物复合片剂。 本发明的特征在于，在第一层中含有乌替卡伦，并且在与第一层分离的附加层中含有降低二十一里烯的稳定性的成分。 该方法是方便的方法，并且通过该方法制备的制剂可以在长期储存期间维持高含量的ubidecarenone，从而同时摄取ubidecarenone和营养成分如各种维生素。

公开(公告)号：US09208880B2

公开(公告)日：2015-12-08

申请号：US14154138

申请日：2014-01-13

Applicant: Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

Inventor： Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC: G11C15/00 ,  G11C15/04 ,  G11C11/404 ,  G11C16/04

CPC classification number: G11C15/04 ,  G11C11/404 ,  G11C15/046 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/10802

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract translation: 内容可寻址存储单元包括第一浮体晶体管和第二浮体晶体管。 第一浮体晶体管和第二浮体晶体管通过公共节点串联电连接。 第一浮体晶体管和第二浮体晶体管存储互补数据。

公开(公告)号：US09029922B2

公开(公告)日：2015-05-12

申请号：US14203235

申请日：2014-03-10

Applicant: Jin-Woo Han ,  Yuniarto Widjaja

Inventor： Jin-Woo Han ,  Yuniarto Widjaja

IPC: H01L29/00 ,  H01L29/78 ,  H01L27/108 ,  G11C16/00

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/407 ,  G11C16/00 ,  G11C16/0416 ,  H01L29/0649 ,  H01L29/7841

Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

Abstract translation: 一种包括电浮体的半导体存储单元。 提供了一种操作存储单元的方法。

公开(公告)号：US20140198551A1

公开(公告)日：2014-07-17

申请号：US14154138

申请日：2014-01-13

Applicant: Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

Inventor： Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C11/404 ,  G11C15/046 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/10802

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract translation: 内容可寻址存储单元包括第一浮体晶体管和第二浮体晶体管。 第一浮体晶体管和第二浮体晶体管通过公共节点串联电连接。 第一浮体晶体管和第二浮体晶体管存储互补数据。

公开(公告)号：US08531330B2

公开(公告)日：2013-09-10

申请号：US13229876

申请日：2011-09-12

Applicant: Kyu-Ha Song ,  Jin-Woo Han ,  Byung-Koo Park ,  Je-Il Jo

Inventor： Kyu-Ha Song ,  Jin-Woo Han ,  Byung-Koo Park ,  Je-Il Jo

IPC: G01S7/28

CPC classification number: G01S7/021

Abstract: A method and device for recognizing a pulse repetition interval (PRI) modulation type of a radar signal are provided. The method for recognizing a pulse repetition interval (PRI) modulation type includes: extracting time of arrival (TOA) information of pulses aligned in time order from a received radar signal; generating a PRI sequence based on a difference of adjacent TOAs in the TOA information of pulses; generating a difference of PRIs (DPRI) sequence by using a difference of the adjacent PRIs in the PRI sequence; generating respective symbol sequences by using specific partition rules from the PRI sequence and the DPRI sequence; and calculating characteristic factors from the symbol sequences, and comparing the characteristic factors with threshold values for discriminating a PRI modulation type to determine the PRI modulation type. Thus, the PRI modulation type, a promising feature for radar signal identification, can be precisely derived.

Abstract translation: 提供了用于识别雷达信号的脉冲重复间隔（PRI）调制类型的方法和装置。 用于识别脉冲重复间隔（PRI）调制类型的方法包括：提取从接收的雷达信号按时间顺序排列的脉冲的到达时间（TOA）信息; 基于脉冲的TOA信息中的相邻TOA的差产生PRI序列; 通过使用PRI序列中的相邻PRI的差异来产生PRI（DPRI）序列的差异; 通过使用来自PRI序列和DPRI序列的特定分区规则来生成各个符号序列; 以及从所述符号序列计算特征因子，以及将所述特征因子与用于鉴别PRI调制类型的阈值进行比较以确定所述PRI调制类型。 因此，可以精确地推导出PRI调制类型，用于雷达信号识别的有希望的特征。