摘要:
In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.
摘要:
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
摘要:
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
摘要:
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
摘要:
A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.
摘要:
A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
摘要:
The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.
摘要:
A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.
摘要:
A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
摘要:
A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.