公开(公告)号：US4415969A

公开(公告)日：1983-11-15

申请号：US119433

申请日：1980-02-07

申请人： John A. Bayliss ,  Stephen R. Colley ,  Roy H. Kravitz ,  William S. Richardson ,  Dorn K. Wilde ,  Gurdev Singh

发明人： John A. Bayliss ,  Stephen R. Colley ,  Roy H. Kravitz ,  William S. Richardson ,  Dorn K. Wilde ,  Gurdev Singh

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/30 ,  G06F9/455 ,  G06F9/00

CPC分类号： G06F9/261 ,  G06F9/268 ,  G06F9/30145

摘要： An instruction translator unit which receives an instruction stream from a main memory of a microprocessor, for latching data fields, for generating microinstructions necessary to emulate the function encoded in an instruction, and for transferring the data and microinstructions to a microinstruction execution unit over an output bus. The instruction unit includes an instruction decoder (ID) which interprets the fields of received instructions and generates single forced microinstructions and starting addresses of multiple-microinstruction routines. A microinstruction sequencer (MIS) accepts the forced microinstructions and the starting addresses and places on the output bus correct microinstruction sequences necessary to execute the received instruction. The microinstruction routines are stored in a read-only memory (ROM) in the MIS. The starting addresses received from the ID are used to index into and to fetch these microinstructions from the ROM. Forced microinstructions bypass the ROM and are transferred directly by the MIS to the execution unit.The ID processes macroinstructions comprised of variable bit length fields by utilizing an extractor in conjunction with a bit pointer (BIP) for stripping off the bits comprising a particular field. The extracted field is presented to a state machine which decodes the particular field and generates data, microinstructions and starting addresses relating to the particular field for use by the MIS. The state machine then updates the BIP by the bit count of the particular field so that it points to the next field to be extracted.

摘要翻译： 指令转换器单元，其接收来自微处理器的主存储器的指令流，用于锁存数据字段，用于产生模拟在指令中编码的功能所必需的微指令，以及用于通过输出将数据和微指令传送到微指令执行单元 总线。 指令单元包括解释接收到的指令的字段的指令解码器（ID），并且生成单个强制微指令和多重微指令程序的起始地址。 微指令定序器（MIS）接受强制微指令和输出总线上的起始地址和位置，正确执行接收指令所需的微指令序列。 微指令例程存储在MIS中的只读存储器（ROM）中。 从ID接收的起始地址用于索引并从ROM获取这些微指令。 强制微指令绕过ROM，并由MIS直接传输到执行单元。 ID通过利用提取器结合位指针（BIP）来处理由可变比特长度字段组成的宏指令，以剥离包含特定字段的比特。 提取的字段被呈现给状态机，该状态机对特定字段进行解码，并生成与MIS使用的特定字段相关的数据，微指令和起始地址。 然后，状态机通过特定字段的位计数来更新BIP，使得它指向要提取的下一个字段。

公开(公告)号：US4407016A

公开(公告)日：1983-09-27

申请号：US235470

申请日：1981-02-18

申请人： John A. Bayliss ,  Craig B. Peterson ,  Doran K. Wilde

发明人： John A. Bayliss ,  Craig B. Peterson ,  Doran K. Wilde

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F13/28 ,  G06F9/20

CPC分类号： G06F13/28 ,  G06F12/1036 ,  G06F12/1441 ,  G06F12/1081

摘要： A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a "window" on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer. Address development and memory response signals are generated by the microprocessor rather than the peripheral subsystem processor for block transfers.

摘要翻译： 微处理器从外围子系统接收地址和数据，用于随后以受控和受保护的方式访问数据处理系统的主存储器的部分。 每个地址用于询问关联存储器以确定地址是否落在主存储器地址空间上的“窗口”的子范围内。 如果地址匹配，则用于在主存储器地址空间上开发相应的地址。 然后，与外围子系统地址相关联的数据通过接口传递到转换的存储器地址的主存储器中。 通过缓冲微处理器上的数据块来改善数据传输。 数据字节以比数据块从缓冲器读出并进入主存储器的速率慢的速率写入缓冲器。 缓冲旁路寄存器允许通过绕过缓冲区将单个字节的数据传输到单个地址。 地址开发和存储器响应信号由微处理器产生，而不是用于块传输的外围子系统处理器。

公开(公告)号：US4315310A

公开(公告)日：1982-02-09

申请号：US79991

申请日：1979-09-28

申请人： John A. Bayliss ,  George W. Cox ,  Bert E. Forbes ,  Kevin C. Kahn

发明人： John A. Bayliss ,  George W. Cox ,  Bert E. Forbes ,  Kevin C. Kahn

IPC分类号： G06F12/02 ,  G06F13/12 ,  G06F13/42 ,  G06F15/16 ,  G06F15/177 ,  G06F3/00

CPC分类号： G06F12/0284 ,  G06F13/128 ,  G06F13/4208

摘要： An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.A function-request facility provides a functional capability over certain objects within the GDP address space.The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.

摘要翻译： 一种用于在外围子系统和广义数据处理器之间提供接口的输入/输出处理器架构。 通过将I / O地址空间的一部分映射到GDP地址空间的一部分，接口处理器能够在两个地址空间（广义数据处理器地址空间和外部处理器I / O地址空间）之间传输数据。 该映射设施为外围子系统提供了一个“窗口”到相关的GDP子系统中。 它接受特定子范围内的地址或子范围，并将其转换为一个或多个GDP数据段的引用。 功能请求功能可以在GDP地址空间内的某些对象上提供功能。 这两个设施将外部处理器上的软件提供到GDP的地址空间中的窗口，使得软件能够通过功能请求装置向GDP发送消息并从其接收消息并且操纵为外部处理器提供的环境 在其地址空间内。

公开(公告)号：US4270167A

公开(公告)日：1981-05-26

申请号：US921082

申请日：1978-06-30

申请人： Robert J. Koehler ,  John A. Bayliss

发明人： Robert J. Koehler ,  John A. Bayliss

IPC分类号： G06F9/38 ,  G06F13/364 ,  G06F15/16

CPC分类号： G06F9/3879 ,  G06F13/364 ,  G06F15/16 ,  G06F9/3877

摘要： The data processing capacity of a practical semiconductor computer system, having both local and system buses, can be expanded both in degree of complexity and magnitude by providing a method and means for cooperatively and concurrently coprocessing digital information among a plurality of processors sharing the same local bus and collectively accessing the system bus as a system unit. In other words, a central processor has primary control and access to a local bus and may have access to a system or common bus shared among many other processors. Also sharing the local bus with the central processor is a plurality of specialized or dedicated processors which are continuously apprised of or actively monitor the internal operational status and operation then being performed by the central processor. The active monitoring of the activity of the other processors sharing the local bus distinguishes these dedicated processors from conventional direct memory accessing processors. Certain ones of the instructions fetched simultaneously by the central processor and the specialized processor from the system memory are reserved for execution in one of the dedicated processors which then shares the local bus with the central processor by means of communicating through a plurality of signals with respect to the status, mode, arbitration, and control of the local bus.

摘要翻译： 具有本地和系统总线的实际半导体计算机系统的数据处理能力可以通过提供一种在共享同一本地的多个处理器之间协同地并且并行地处理数字信息的方法和装置来扩展复杂性和大小的程度 总线和集体访问系统总线作为系统单元。 换句话说，中央处理器具有对本地总线的主要控制和访问，并且可以访问在许多其他处理器之间共享的系统或公共总线。 还与中央处理器共享本地总线是多个专用或专用处理器，其被连续地通知或主动地监视由中央处理器执行的内部操作状态和操作。 共享本地总线的其他处理器的活动的主动监视将这些专用处理器与传统的直接存储器访问处理器区分开来。 中央处理器和专用处理器从系统存储器同时取出的指令中的某些指令被保留用于在专用处理器之一中执行，然后专用处理器与中央处理器共享本地总线，借助于通过多个信号进行通信 对当地公共汽车的状态，模式，仲裁和控制。

公开(公告)号：US4063409A

公开(公告)日：1977-12-20

申请号：US646591

申请日：1976-01-05

申请人： John A. Bayliss

发明人： John A. Bayliss

IPC分类号： G04F10/00 ,  G04F10/04 ,  G04G5/04 ,  G04G9/08 ,  G04G99/00 ,  G04C3/00

CPC分类号： G04G99/006 ,  G04F10/04 ,  G04G5/045 ,  G04G9/085

摘要： A random access memory is combined with a programmable logic array to count time pulses within an integrated circuit watch. A master oscillator drives the internal timing clocks and serves as a time standard for a timing and control circuit means which manipulates data within the random access memory. The timing and control circuit may contain a programmable read-only memory so that words stored within the random access memory may be read, and manipulated, in a selected sequence. The programmable logic array increments the word selectively read from the random access memory, compares it to a limit value and generates one or more flags according to the desired data manipulation. Words stored within the random access memory may be selectively displayed by a liquid crystal display or light emitting diode display in a selected format determined by the programmable read-only memory. A driver circuit coupled to the display may also contain a read-only memory so that the data may be displayed in a selected one of plurality of display fonts. The operational and display modes may be customized by appropriately modifying the programmable logic array and read-only memories without altering the system architecture.

摘要翻译： 随机存取存储器与可编程逻辑阵列组合以对集成电路表内的时间脉冲进行计数。 主振荡器驱动内部定时时钟，并且用作对随机存取存储器内的数据进行操作的定时和控制电路装置的时间标准。 定时和控制电路可以包含可编程只读存储器，使得存储在随机存取存储器内的字可以以选定的顺序读取和操纵。 可编程逻辑阵列增加从随机存取存储器中选择性读取的字，将其与极限值进行比较，并根据所需的数据操作生成一个或多个标志。 可以通过由可编程只读存储器确定的所选格式的液晶显示器或发光二极管显示器来选择性地显示存储在随机存取存储器内的字。 耦合到显示器的驱动器电路还可以包含只读存储器，使得数据可以以多个显示字体中的所选择的一个显示。 可以通过适当地修改可编程逻辑阵列和只读存储器而不改变系统架构来定制操作和显示模式。