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    Method to fabricate a nanowire CHEMFET sensor device using selective nanowire deposition
    2.
    发明授权
    Method to fabricate a nanowire CHEMFET sensor device using selective nanowire deposition 失效
    使用选择性纳米线沉积制造纳米线CHEMFET传感器器件的方法

    公开(公告)号：US07309621B2

    公开(公告)日：2007-12-18

    申请号：US11115814

    申请日：2005-04-26

    申请人： John F. Conley, Jr. ,  Yoshi Ono ,  Lisa H. Stecker

    发明人： John F. Conley, Jr. ,  Yoshi Ono ,  Lisa H. Stecker

    IPC分类号： H01L51/40 ,  H01L21/00 ,  H01L21/8238

    CPC分类号： G01N27/4146 ,  B82Y10/00 ,  B82Y15/00 ,  G11C2213/16 ,  H01L51/0048 ,  H01L51/0545

    摘要： A method of fabricating a nanowire CHEMFET sensor mechanism includes preparing a silicon substrate; depositing a polycrystalline ZnO seed layer on the silicon substrate; patterning and etching the polycrystalline ZnO seed layer; depositing an insulating layer over the polycrystalline ZnO seed layer and the silicon substrate; patterning and etching the insulating layer to form contact holes to a source region and a drain region; metallizing the contact holes to form contacts for the source region and the drain region; depositing a passivation dielectric layer over the insulating layer and the contacts; patterning the passivation layer and etching to expose the polycrystalline ZnO seed layer between the source region and the drain region; and growing ZnO nanostructures on the exposed ZnO seed layer to form a ZnO nanostructure CHEMFET sensor device.

    摘要翻译： 制造纳米线CHEMFET传感器机构的方法包括制备硅衬底; 在硅衬底上沉积多晶ZnO种子层; 图案化和蚀刻多晶ZnO种子层; 在多晶ZnO种子层和硅衬底上沉积绝缘层; 图案化和蚀刻绝缘层以形成到源极区域和漏极区域的接触孔; 金属化接触孔以形成用于源极区域和漏极区域的触点; 在所述绝缘层和所述触点上沉积钝化介电层; 图案化钝化层并蚀刻以在源极区域和漏极区域之间暴露多晶ZnO晶种层; 并在曝光的ZnO种子层上生长ZnO纳米结构以形成ZnO纳米结构CHEMFET传感器装置。

    System and method for integrating multiple metal gates for CMOS applications
    4.
    发明授权
    System and method for integrating multiple metal gates for CMOS applications 失效
    用于集成多个金属栅极用于CMOS应用的系统和方法

    公开(公告)号：US06873048B2

    公开(公告)日：2005-03-29

    申请号：US10376795

    申请日：2003-02-27

    申请人： Wei Gao ,  John F. Conley, Jr. ,  Yoshi Ono

    发明人： Wei Gao ,  John F. Conley, Jr. ,  Yoshi Ono

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L23/48

    CPC分类号： H01L29/66583 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer first thickness; selectively removing the second metal layer overlying the first channel region; forming a third metal layer; establishing a first MOSFET with a gate work function responsive to the thicknesses of the first and third metal layer overlying the first channel region; and, establishing a second MOSFET, complementary to the first MOSFET, with a gate work function responsive to the combination of the thicknesses of the first, second, and third metal layers overlying the second channel region.

    摘要翻译： 提供了具有金属栅极的双栅极MOSFET和用于设置这种MOSFET中的阈值电压的方法。 该方法包括：形成覆盖第一和第二沟道区的栅极氧化层; 形成具有覆盖所述栅极氧化物层的第一厚度的第一金属层; 形成具有覆盖所述第一金属层第一厚度的第二厚度的第二金属层; 选择性地去除覆盖在第一沟道区上的第二金属层; 形成第三金属层; 建立具有响应于覆盖在第一沟道区上的第一和第三金属层的厚度的栅极功函数的第一MOSFET; 以及响应于覆盖在第二沟道区上的第一，第二和第三金属层的厚度的组合，建立与第一MOSFET互补的第二MOSFET。

    Method to manipulate selectivity of a metal oxide sensor
    5.
    发明授权
    Method to manipulate selectivity of a metal oxide sensor 失效
    操纵金属氧化物传感器选择性的方法

    公开(公告)号：US07528695B2

    公开(公告)日：2009-05-05

    申请号：US11361519

    申请日：2006-02-23

    申请人： John F. Conley, Jr. ,  Yoshi Ono

    发明人： John F. Conley, Jr. ,  Yoshi Ono

    IPC分类号： H01C7/00

    CPC分类号： G01N33/0027

    摘要： A method of selectively enhancing the sensitivity of a metal oxide sensor includes fabricating a ZnO sensor having a ZnO sensor element therein; and exposing the ZnO sensor element to a plasma stream.

    摘要翻译： 选择性提高金属氧化物传感器的灵敏度的方法包括制造其中具有ZnO传感器元件的ZnO传感器; 并将ZnO传感器元件暴露于等离子体流。

    Reactive gate electrode conductive barrier
    6.
    发明授权
    Reactive gate electrode conductive barrier 有权
    无源栅电极导电屏障

    公开(公告)号：US07473640B2

    公开(公告)日：2009-01-06

    申请号：US10784662

    申请日：2004-02-23

    申请人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao

    发明人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao

    IPC分类号： H01L29/72

    CPC分类号： H01L21/28079 ,  H01L21/823842 ,  H01L29/4958

    摘要： A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.

    摘要翻译： 提供了一种方法和相应的晶体管结构，用于保护栅极免受下层栅极绝缘体的影响。 该方法包括：形成覆盖沟道区的栅极绝缘体; 形成覆盖栅极绝缘体的厚度小于5纳米（nm）的第一金属屏障; 形成覆盖所述第一金属屏障的第二金属栅电极，其厚度大于10nm; 并且建立专门响应于第二金属的栅电极功函数。 第二金属栅电极可以是以下材料之一：元素金属，例如p + poly，n + poly。 Ta，W，Re，RuO 2，Pt，Ti，Hf，Zr，Cu，V，Ir，Ni，Mn，Co，NbO，Pd，Mo，TaSiN和Nb，二元金属如WN，TaN和TiN 。 第一金属屏障可以是二元金属，例如TaN，TiN或WN。

    Method to perform selective atomic layer deposition of zinc oxide
    7.
    发明授权
    Method to perform selective atomic layer deposition of zinc oxide 有权
    执行氧化锌选择性原子层沉积的方法

    公开(公告)号：US07160819B2

    公开(公告)日：2007-01-09

    申请号：US11114862

    申请日：2005-04-25

    申请人： John F. Conley, Jr. ,  Yoshi Ono ,  David R. Evans

    发明人： John F. Conley, Jr. ,  Yoshi Ono ,  David R. Evans

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0228 ,  C23C16/042 ,  C23C16/407 ,  C23C16/45525 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/3141

    摘要： A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and deionized water; depositing a layer of ZnO on the wafer by ALD using diethyl zinc and H2O at a temperature of between about 140° C. to 170° C.; and removing the blocking agent from the wafer.

    摘要翻译： 在准备硅晶片的晶片上的ZnO的选择性ALD的方法; 在其中要抑制ZnO沉积的选定区域中用封闭剂对硅晶片进行图案化，其中封闭剂取自一组封闭剂，包括异丙醇，丙酮和去离子水; 在约140℃至170℃的温度下，使用二乙基锌和H 2 O 2，通过ALD在晶片上沉积ZnO层。 并从晶片上除去封闭剂。

    Methods of forming a microlens array over a substrate employing a CMP stop
    8.
    发明授权
    Methods of forming a microlens array over a substrate employing a CMP stop 失效
    在使用CMP停止的衬底上形成微透镜阵列的方法

    公开(公告)号：US07029944B1

    公开(公告)日：2006-04-18

    申请号：US10956789

    申请日：2004-09-30

    申请人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao ,  David R. Evans

    发明人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao ,  David R. Evans

    IPC分类号： H01L21/00

    CPC分类号： H01L21/31053 ,  H01L21/31133 ,  H01L27/14627 ,  H01L27/14685

    摘要： A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array. An embodiment of the method comprises providing a substrate having a surface with photo-elements on the surface; depositing a transparent material overlying the surface of the substrate; depositing a CMP stop overlying the transparent material; depositing a lens-shaping layer overlying the CMP stop layer; depositing and patterning a photoresist layer overlying the lens-shaping layer to form openings to expose the lens-shaping layer; introducing a first isotropic etchant into the openings and etching the lens-shaping layer where exposed to form initial lens shapes having a radius; stripping the photoresist; exposing the lens-shaping layer to a second isotropic etchant to increase the radius of the lens shapes; transferring the lens shape through the CMP stop layer into the transparent material using an anisotropic etch; and depositing a lens material overlying the transparent material, whereby the lens shapes are at least partially filled with lens material. Planarizing the lens material using CMP and stopping at the CMP stop layer.

    摘要翻译： 提供一种形成微透镜结构的方法以及采用微透镜阵列的CCD阵列结构。 该方法的一个实施例包括提供具有在表面上具有光元件的表面的基底; 沉积覆盖衬底表面的透明材料; 沉积覆盖透明材料的CMP停止点; 沉积覆盖CMP停止层的透镜成形层; 沉积和图案化覆盖透镜成形层的光致抗蚀剂层以形成露出透镜成形层的开口; 在开口中引入第一各向同性蚀刻剂并蚀刻暴露于其中形成具有半径的初始透镜形状的透镜成形层; 剥离光刻胶; 将透镜成形层暴露于第二各向同性蚀刻剂以增加透镜形状的半径; 使用各向异性蚀刻将透镜形状通过CMP停止层转移到透明材料中; 以及沉积覆盖透明材料的透镜材料，由此透镜形状至少部分地被透镜材料填充。 使用CMP对透镜材料进行平面化，并在CMP停止层处停止。

    Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same
    10.
    发明授权
    Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same 有权
    铽掺杂，富硅氧化物电致发光器件及其制造方法

    公开(公告)号：US07811837B2

    公开(公告)日：2010-10-12

    申请号：US11582275

    申请日：2006-10-16

    申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

    IPC分类号： H01L29/00

    CPC分类号： H01L27/15 ,  H01L33/0004 ,  H01L33/343

    摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

    摘要翻译： 一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。 根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。