公开(公告)号：US4743563A

公开(公告)日：1988-05-10

申请号：US53917

申请日：1987-05-26

申请人： James R. Pfiester ,  John R. Alvis ,  Orin W. Holland

发明人： James R. Pfiester ,  John R. Alvis ,  Orin W. Holland

IPC分类号： H01L21/225 ,  H01L21/316 ,  H01L21/762 ,  H01L27/092 ,  H01L21/265 ,  H01L21/22

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/2255 ,  H01L21/31662 ,  H01L21/76213 ,  H01L27/092 ,  Y10S148/082 ,  Y10S438/981

摘要： A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS device structure. In accordance with one embodiment of the invention a silicon substrate is provided which has first and second regions of opposite conductivity type. A uniform doping such as by ion implantation is provided into each of the conductivity regions. The two regions or portions thereof are then simultaneously differently oxidized to cause a differential segregation of the dopant into the thermally grown oxide. The differential oxide growth can be achieved by selectively implanting halogen ions into the wafer surface prior to the thermal oxidation.

摘要翻译： 公开了一种用于控制半导体器件的两个区域的表面掺杂的方法，更具体地说是用于在CMOS器件结构中实现必要的场掺杂的这种控制。 根据本发明的一个实施例，提供了具有相反导电类型的第一和第二区域的硅衬底。 在每个导电区域中提供诸如通过离子注入的均匀掺杂。 然后，两个区域或其部分被同时不同地氧化，以引起掺杂剂与热生长的氧化物的差异偏析。 可以通过在热氧化之前将卤素离子选择性地注入晶片表面来实现差异氧化物生长。

公开(公告)号：US4728619A

公开(公告)日：1988-03-01

申请号：US63934

申请日：1987-06-19

申请人： James R. Pfiester ,  John R. Alvis ,  Orin W. Holland

发明人： James R. Pfiester ,  John R. Alvis ,  Orin W. Holland

IPC分类号： H01L21/22 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/263

CPC分类号： H01L21/22 ,  H01L21/76218 ,  H01L21/823878 ,  H01L27/0928

摘要： A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.

摘要翻译： 互补金属氧化物半导体（CMOS）隔离结构，其中不同导电类型的相邻区域之间的场隔离结构具有掺杂有受锗影响的硼或磷的沟道阻挡层。 锗和选自磷和硼的二次掺杂物的双重用途提供了更精确地放置的通道阻挡，因为锗阻碍了硼和磷的扩散，并且令人惊讶地为其中的器件提供了改进的宽度效应，其中 通道停止。 或者，可以以这样的方式放置锗，以避免将硼或磷吸收到场氧化物中，并阻止其在不希望的不同导电类型的阱上的扩散。

公开(公告)号：US4748134A

公开(公告)日：1988-05-31

申请号：US53919

申请日：1987-05-26

申请人： Orin W. Holland ,  John R. Alvis

发明人： Orin W. Holland ,  John R. Alvis

IPC分类号： H01L21/265 ,  H01L21/316

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662

摘要： An improved process is disclosed for forming the field oxide which provides isolation between adjacent devices in an integrated circuit. In one embodiment of the invention the improvement includes implanting halogen ions, and preferably chlorine ions, into the selected regions of a semiconductor substrate where field oxide is to be formed. The halogen ions are implanted before the field oxide is thermally grown and result in a localized enhancement of the oxide growth rate in the vertical direction compared to the lateral direction. For a given oxidation cycle, the halogen implant results in the growth of a thicker oxide with minimum lateral encroachment.

摘要翻译： 公开了一种改进的方法，用于形成场集成电路中的相邻器件之间的隔离的场氧化物。 在本发明的一个实施例中，改进包括将卤素离子，优选氯离子注入到要形成场氧化物的半导体衬底的选定区域中。 在场氧化物热生长之前注入卤素离子，并且导致与横向方向相比在垂直方向上的氧化物生长速率的局部增强。 对于给定的氧化循环，卤素注入导致较厚的氧化物的生长，具有最小的横向侵入。

公开(公告)号：US4928156A

公开(公告)日：1990-05-22

申请号：US319000

申请日：1989-03-06

申请人： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

发明人： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/7836 ,  Y10S257/919

摘要： Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

摘要翻译： 具有n型源极/漏极区域的金属氧化物半导体（MOS）晶体管在源/漏极中或附近也具有锗掺杂区域。 分级源极漏极（GSD），轻掺杂漏极（LDD）和双扩散漏极（DDD）中磷附近或位置处的锗的存在提供了漏极区的更好的轮廓，其结点深度低于磷获得的结点深度 或特别是磷和砷一起。 获得漏极结的良好分级，以避免热载流子不稳定或热载流子注入问题，同时连接浅源极结，这可以最大限度地减小横向掺杂剂扩散，并减小GSD和LDD中n +和n +区之间的距离。

公开(公告)号：US4704367A

公开(公告)日：1987-11-03

申请号：US853840

申请日：1986-04-21

申请人： John R. Alvis ,  Orin W. Holland

发明人： John R. Alvis ,  Orin W. Holland

IPC分类号： H01L21/3215 ,  H01L21/265

CPC分类号： H01L21/3215 ,  Y10S148/14 ,  Y10S438/937

摘要： A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.

摘要翻译： 通过氩气注入通过多个热循环来抑制集成电路上的金属膜的小丘生长的技术。 虽然众所周知，许多物质如砷的离子注入通过一个热循环抑制金属膜中的小丘的生长，但是发现只有一个所提出的离子氩就可以抑制多个后续热循环的小丘形成。 对于其他物种，小丘形成将在多个周期后再次发生。 这种特性对于防止层间短路的双层金属（DLM）工艺很重要。

公开(公告)号：US4837173A

公开(公告)日：1989-06-06

申请号：US72932

申请日：1987-07-13

申请人： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

发明人： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/7836

摘要： Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.

摘要翻译： 具有n型源极/漏极区域的金属氧化物半导体（MOS）晶体管在源/漏极中或附近也具有锗掺杂区域。 分级源极漏极（GSD），轻掺杂漏极（LDD）和双扩散漏极（DDD）中磷附近或位置处的锗的存在提供了漏极区的更好的轮廓，其结点深度低于磷获得的结点深度 或特别是磷和砷一起。 获得漏极结的良好分级，以避免热载流子不稳定或热载流子注入问题，同时连接浅源极结，这可以最大限度地减小横向掺杂剂扩散，并减小GSD和LDD中n +和n +区之间的距离。

公开(公告)号：US20130313668A1

公开(公告)日：2013-11-28

申请号：US13479668

申请日：2012-05-24

申请人： Gregory S. Spencer ,  John R. Alvis ,  Hsiao-Hui Chen ,  Joseph F. Orcutt ,  Srivatsa G. Kundalgurki

发明人： Gregory S. Spencer ,  John R. Alvis ,  Hsiao-Hui Chen ,  Joseph F. Orcutt ,  Srivatsa G. Kundalgurki

IPC分类号： H01L27/144 ,  H01L31/18

CPC分类号： G02B6/43 ,  H01L31/02325

摘要： A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.

摘要翻译： 光电设备包括具有通过基板的开口的基板。 所述光电设备还包括在所述基板上方的包括在所述开口上方的绝缘层。 光电设备还包括绝缘层上的有源层。 光电设备还包括形成在有源层中的光活性器件，其中光活性器件在开口之上。 光电设备还包括形成在有源层中的有源电子电路。 光电设备还包括在开口中的绝缘层上的反射层。

公开(公告)号：US5279978A

公开(公告)日：1994-01-18

申请号：US993282

申请日：1992-12-18

申请人： Yee-Chaung See ,  Thomas C. Mele ,  John R. Alvis

发明人： Yee-Chaung See ,  Thomas C. Mele ,  John R. Alvis

IPC分类号： H01L27/06 ,  H01L27/12 ,  H01L21/265

CPC分类号： H01L27/1203 ,  H01L27/0623 ,  Y10S148/009

摘要： A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer.In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region. An NMOS and a PMOS transistor are formed in the thin MOS region and are separated by a third isolation region extending from the first surface to the buried oxide layer. A vertical bipolar is formed in the electrically insulated bipolar region of the epitaxial layer.

摘要翻译： 公开了一种BiCMOS器件和工艺，其中晶体管元件制造在SOI衬底上。 使用SIMOX工艺在单晶硅衬底中形成掩埋氧化层，接着进行外延沉积，以形成覆盖掩埋氧化物层的不同厚度的硅体。 然后在外延层的薄部分中形成MOS晶体管，并且在外延层的厚部分中形成垂直双极晶体管。 根据本发明的一个实施例，提供单晶半导体衬底，其具有在第一表面下面的主表面和掩埋氧化物层。 具有薄MOS区和厚双极区的第一导电类型的轻掺杂外延层覆盖在主表面上。 从第一表面延伸到掩埋氧化物层的第一和第二隔离区域将双极区域与MOS区域分离并电绝缘。 NMOS和PMOS晶体管形成在薄MOS区中，并由从第一表面延伸到掩埋氧化物层的第三隔离区隔开。 在外延层的电绝缘双极区域中形成垂直双极。

公开(公告)号：US5212397A

公开(公告)日：1993-05-18

申请号：US566901

申请日：1990-08-13

申请人： Yee-Chaung See ,  Thomas C. Mele ,  John R. Alvis

发明人： Yee-Chaung See ,  Thomas C. Mele ,  John R. Alvis

IPC分类号： H01L27/06 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/0623 ,  Y10S148/009

摘要： A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer. In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region. An NMOS and a PMOS transistor are formed in the thin MOS region and are separated by a third isolation region extending from the first surface to the buried oxide layer. A vertical bipolar is formed in the electrically insulated bipolar region of the epitaxial layer.

摘要翻译： 公开了一种BiCMOS器件和工艺，其中晶体管元件制造在SOI衬底上。 使用SIMOX工艺在单晶硅衬底中形成掩埋氧化层，接着进行外延沉积，以形成覆盖掩埋氧化物层的不同厚度的硅体。 然后在外延层的薄部分中形成MOS晶体管，并且在外延层的厚部分中形成垂直双极晶体管。 根据本发明的一个实施例，提供单晶半导体衬底，其具有在第一表面下面的主表面和掩埋氧化物层。 具有薄MOS区和厚双极区的第一导电类型的轻掺杂外延层覆盖在主表面上。 从第一表面延伸到掩埋氧化物层的第一和第二隔离区域将双极区域与MOS区域分离并电绝缘。 NMOS和PMOS晶体管形成在薄MOS区中，并由从第一表面延伸到掩埋氧化物层的第三隔离区隔开。 在外延层的电绝缘双极区域中形成垂直双极。

公开(公告)号：US07998822B2

公开(公告)日：2011-08-16

申请号：US12244413

申请日：2008-10-02

申请人： Dharmesh Jawarani ,  John R. Alvis ,  Michael G. Harrison ,  Leo Mathew ,  John E. Moore ,  Rode R. Mora

发明人： Dharmesh Jawarani ,  John R. Alvis ,  Michael G. Harrison ,  Leo Mathew ,  John E. Moore ,  Rode R. Mora

IPC分类号： H01L21/336

CPC分类号： H01L21/28518 ,  H01L21/2855

摘要： A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.

摘要翻译： 半导体制造工艺包括形成覆盖在晶片（101）的半导体衬底（104）上的栅极电介质（114）上的栅电极（112）和包括垂直部分（118）的衬垫电介质层（116） 栅电极和覆盖在半导体衬底（104）的上表面上的水平部分（117）。 邻近垂直部分（118）并且覆盖衬里介电层（116）的水平部分（117）形成间隔物（108）。 在形成间隔物（108）之后，去除衬里电介质层（116）的暴露部分以形成被延伸间隔物（108）覆盖的衬里电介质结构（126）。 然后将延伸垫片（108）回蚀刻以露出或揭开衬垫介质结构（126）的四肢。 在蚀刻回间隔物（108）之前，金属（130）可以溅射沉积在晶片（101）上，准备形成硅化物（134）。 在蚀刻之后，晶片（101）可以浸入食人鱼溶液中并用氩气的RF溅射（140）清洁。