NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME
    4.
    发明申请
    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME 有权
    深层次微电解法半导体集成电路中导电线路的微结构和界面粗糙度的非破坏性评估

    公开(公告)号:US20070130551A1

    公开(公告)日:2007-06-07

    申请号:US11673369

    申请日:2007-02-09

    IPC分类号: G06F17/50

    摘要: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

    摘要翻译: 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后,基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后,基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME
    5.
    发明申请
    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME 有权
    深层次微电解法半导体集成电路中导电线路的微结构和界面粗糙度的非破坏性评估

    公开(公告)号:US20060071676A1

    公开(公告)日:2006-04-06

    申请号:US10711418

    申请日:2004-09-17

    IPC分类号: G01R31/26

    摘要: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

    摘要翻译: 用于评估半导体集成电路中的线路的新型结构和方法。 可以在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后,基于所有线的所有部分的电阻来确定第一线几何形状调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后,可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

    Implied presence detection in a communication system
    8.
    发明申请
    Implied presence detection in a communication system 审中-公开
    在通信系统中隐含存在检测

    公开(公告)号:US20070130323A1

    公开(公告)日:2007-06-07

    申请号:US11292645

    申请日:2005-12-02

    IPC分类号: G06F15/173

    CPC分类号: H04L67/24 H04L67/22

    摘要: The present invention provides for systems and methods for determining the likelihood that an intended recipient is currently available to communicate via at least one communication mechanism. A presence module monitors the computer usage activity of the intended recipient. The data relating to the computer usage activity of the intended recipient is stored in a database, and is later utilized by a processing module for determining the likelihood that the intended recipient is currently available to communicate via the at least one communication mechanism. The likelihood that the intended recipient is currently available to communicate via the at least one communication mechanism is displayed to at least one other user by an interface module. A communication module is configured to send a message to the intended recipient via the at least one communication mechanism.

    摘要翻译: 本发明提供了用于确定预期接收者当前可用于经由至少一个通信机制进行通信的可能性的系统和方法。 存在模块监视预期收件人的计算机使用活动。 与预期接收者的计算机使用活动相关的数据被存储在数据库中,并且稍后由处理模块用于确定预期接收者当前可用于经由至少一个通信机制进行通信的可能性。 预期接收者当前可用于通过至少一个通信机制进行通信的可能性由接口模块显示给至少一个其他用户。 通信模块被配置为经由所述至少一个通信机制向预期接收者发送消息。

    Federated challenge credit system
    9.
    发明申请
    Federated challenge credit system 有权
    联合挑战信用制度

    公开(公告)号:US20060242244A1

    公开(公告)日:2006-10-26

    申请号:US11098333

    申请日:2005-04-04

    IPC分类号: G06F15/16

    CPC分类号: G06Q10/107 H04L51/12

    摘要: Systems and methods for reducing the number of challenge messages that are sent in response to an incoming message in situations where the incoming message is likely not unsolicited. The systems and methods include evaluating the behavior of a sender with regard to one or more federated messaging services and determining if the sender is approved or unapproved. If the sender is approved, the incoming message is deliver to a recipient's inbox without issuing a challenge message. Unapproved senders are required to respond to a challenge message.

    摘要翻译: 用于减少在传入消息可能未被请求的情况下响应于传入消息而发送的质询消息的数量的系统和方法。 系统和方法包括评估发送者关于一个或多个联合消息传递服务的行为,并确定发送者是否被批准或未被批准。 如果发件人被批准,传入的消息将传递到收件人的收件箱,而不发出质询消息。 未经批准的发件人需要回复挑战消息。