Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same
    6.
    发明授权
    Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same 有权
    制造非易失性存储器集成电路器件的方法和使用其制造的非易失性存储器集成电路器件

    公开(公告)号:US08030150B2

    公开(公告)日:2011-10-04

    申请号:US12397543

    申请日:2009-03-04

    IPC分类号: H01L21/8238

    摘要: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

    摘要翻译: 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构,并且每个都具有堆叠下部结构,导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案,从中去除第一牺牲层图案,从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面,第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

    Method of Fabricating Non-Volatile Memory Integrated Circuit Device and Non-Volatile Memory Integrated Circuit Device Fabricated Using the Same
    7.
    发明申请
    Method of Fabricating Non-Volatile Memory Integrated Circuit Device and Non-Volatile Memory Integrated Circuit Device Fabricated Using the Same 有权
    制造非易失性存储器集成电路器件和使用其的非易失性存储器集成电路器件的方法

    公开(公告)号:US20080017915A1

    公开(公告)日:2008-01-24

    申请号:US11763137

    申请日:2007-06-14

    IPC分类号: H01L27/105 H01L21/8229

    摘要: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

    摘要翻译: 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构,并且每个都具有堆叠下部结构,导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案,从中去除第一牺牲层图案,从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面,第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

    Semiconductor device including dummy gate part and method of fabricating the same
    9.
    发明申请
    Semiconductor device including dummy gate part and method of fabricating the same 有权
    半导体器件包括伪栅极部分及其制造方法

    公开(公告)号:US20090121296A1

    公开(公告)日:2009-05-14

    申请号:US12291211

    申请日:2008-11-07

    IPC分类号: H01L27/10

    摘要: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

    摘要翻译: 在可靠的半导体器件和制造半导体器件的方法中,通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差(也称为电平差)。 半导体器件包括:半导体衬底,包括单元区域和围绕单元区域的周边区域;多个虚设有源区域,被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件,形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域,其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

    Method of Fabricating Semiconductor Device
    10.
    发明申请
    Method of Fabricating Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号:US20080045019A1

    公开(公告)日:2008-02-21

    申请号:US11833050

    申请日:2007-08-02

    IPC分类号: H01L21/302

    CPC分类号: H01L29/66795 H01L29/7851

    摘要: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

    摘要翻译: 公开了一种制造包括多栅极晶体管的半导体器件的方法。 制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件,被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。