摘要:
In one aspect, a chemical-mechanical-polishing (CMP) slurry composition is provided which includes ceria abrasive contained in a solution, where the solution includes a viscosity increasing agent which includes a non-ionic polymer compound, and where a viscosity of the composition is at least 1.5 cP. In other aspects, the viscosity increasing agent includes one or more of poly(ethyleneglycol), a Gum compound and isopropyl alcohol.
摘要:
A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要:
A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要:
A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要:
A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
摘要:
A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.
摘要:
A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.
摘要:
A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.
摘要:
In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
摘要:
Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.