公开(公告)号：US10235258B2

公开(公告)日：2019-03-19

申请号：US14683705

申请日：2015-04-10

申请人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

发明人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

IPC分类号： G06F11/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G06F11/10 ,  G11C29/04

摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

公开(公告)号：US09001601B2

公开(公告)日：2015-04-07

申请号：US13601725

申请日：2012-08-31

申请人： Jong-pil Son ,  Chul-woo Park

发明人： Jong-pil Son ,  Chul-woo Park

IPC分类号： G11C29/00 ,  G11C29/44

CPC分类号： G11C29/808 ,  G11C29/4401 ,  G11C2029/4402

摘要： A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell.

摘要翻译： 存储器件包括修复电路，该修复电路包括故障位位置信息表，其被配置为存储存储单元阵列的正常区域中的有缺陷单元的行和列地址。 修复电路还包括行地址比较单元，其被配置为将缺陷单元的行地址与从外部接收的第一存取单元的行地址进行比较，并且当缺陷单元的行地址匹配时输出第一行匹配信号 第一接入小区的行地址，以及列地址比较单元，被配置为将缺陷小区的列地址与从外部接收的第一接入小区的列地址进行比较，并且如果列 故障小区的地址与第一接入小区的列地址相同。

公开(公告)号：US20140317469A1

公开(公告)日：2014-10-23

申请号：US14208795

申请日：2014-03-13

申请人： Young-soo Sohn ,  Kwang-il Park ,  Chul-woo Park ,  Jong-pil Son ,  Jae-youn Youn ,  Hoi-ju Chung

发明人： Young-soo Sohn ,  Kwang-il Park ,  Chul-woo Park ,  Jong-pil Son ,  Jae-youn Youn ,  Hoi-ju Chung

IPC分类号： G06F11/10 ,  G11C29/10

CPC分类号： G06F11/1068 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1052 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/808 ,  G11C29/848 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208

摘要： Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

摘要翻译： 提供了执行ECC操作和冗余修复操作的存储器件和存储器模块。 存储器件通过使用纠错码（ECC）操作来修复由于“故障”单元而导致的单位错误，并且当“失败”单元不可修复时，通过使用冗余修复操作来修复“失败”单元 通过ECC操作。 冗余修复操作包括数据线修复和块修复。 ECC操作可以改变对应于包括“失败”单元的每单位存储器单元的数据的码字，并且还可以改变关于改变的码字的奇偶校验位的大小。

公开(公告)号：US08638621B2

公开(公告)日：2014-01-28

申请号：US13413938

申请日：2012-03-07

申请人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/00 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

摘要翻译： 一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。 感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

公开(公告)号：US20120230139A1

公开(公告)日：2012-09-13

申请号：US13413938

申请日：2012-03-07

申请人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/06 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

摘要翻译： 一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。 感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

公开(公告)号：US09183909B2

公开(公告)日：2015-11-10

申请号：US13585449

申请日：2012-08-14

申请人： Jong-pil Son

发明人： Jong-pil Son

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C7/24

CPC分类号： G11C11/16 ,  G11C7/24 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A non-volatile semiconductor memory device includes: a power supply unit; a memory cell array powered on or off by the power supply unit; and a read unit for reading data recorded on the memory cell array, wherein the data recorded on the memory cell array is not read in response to a control signal, when the memory cell array is powered on or off.

摘要翻译： 非易失性半导体存储器件包括：电源单元; 由电源单元供电或关闭的存储单元阵列; 以及读取单元，用于读取记录在存储单元阵列上的数据，其中当存储单元阵列通电或断开时，不响应于控制信号读取记录在存储单元阵列上的数据。

公开(公告)号：US08482989B2

公开(公告)日：2013-07-09

申请号：US13295484

申请日：2011-11-14

申请人： Jong-pil Son ,  Seong-jin Jang ,  Byung-sik Moon ,  Ju-seop Park

发明人： Jong-pil Son ,  Seong-jin Jang ,  Byung-sik Moon ,  Ju-seop Park

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C17/14 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.

摘要翻译： 提供一种包括熔丝的半导体器件及其操作方法。 半导体器件包括熔丝阵列，第一寄存器单元和第二寄存器单元。 熔丝阵列包括多个行和列。 第一寄存器单元从熔丝阵列接收至少一行熔丝数据。 至少一行熔丝数据的保险丝数据由第一寄存器单元并行接收。 第二寄存器单元从第一寄存器单元一次接收至少一个位的熔丝数据。

公开(公告)号：US20130163355A1

公开(公告)日：2013-06-27

申请号：US13611084

申请日：2012-09-12

申请人： Jong-pil Son ,  Young-soo Sohn

发明人： Jong-pil Son ,  Young-soo Sohn

IPC分类号： G11C29/44

CPC分类号： G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

摘要： A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

公开(公告)号：US20130051132A1

公开(公告)日：2013-02-28

申请号：US13585449

申请日：2012-08-14

申请人： Jong-pil Son

发明人： Jong-pil Son

IPC分类号： G11C11/16

CPC分类号： G11C11/16 ,  G11C7/24 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A non-volatile semiconductor memory device includes: a power supply unit; a memory cell array powered on or off by the power supply unit; and a read unit for reading data recorded on the memory cell array, wherein the data recorded on the memory cell array is not read in response to a control signal, when the memory cell array is powered on or off.

摘要翻译： 非易失性半导体存储器件包括：电源单元; 由电源单元供电或关闭的存储单元阵列; 以及读取单元，用于读取记录在存储单元阵列上的数据，其中当存储单元阵列通电或断开时，不响应于控制信号读取记录在存储单元阵列上的数据。

公开(公告)号：US08929165B2

公开(公告)日：2015-01-06

申请号：US13611084

申请日：2012-09-12

申请人： Jong-pil Son ,  Young-soo Sohn

发明人： Jong-pil Son ,  Young-soo Sohn

IPC分类号： G11C8/00 ,  G11C11/408 ,  G11C29/04 ,  G11C29/00 ,  G11C16/08

CPC分类号： G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

摘要： A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

摘要翻译： 一种存储器件，包括：存储单元阵列，包括正常存储单元和排列成行和列的备用存储单元，所述备用存储单元包括包括常规存储单元的常规列和至少一个备用存储单元的备用列，段匹配确定电路， 段地址，其中行地址信息对应于故障段并产生负载控制信号;以及列匹配确定电路，配置为响应于具有列地址的负载控制信号将对应于故障列的列地址信息进行比较，并产生 列地址替换控制信号，其中响应于列地址替换控制信号，连接到故障段的故障列的存储器单元被连接到备用存储器单元的列的存储器单元替换。