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    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20130163355A1

    公开(公告)日：2013-06-27

    申请号：US13611084

    申请日：2012-09-12

    申请人： Jong-pil Son ,  Young-soo Sohn

    发明人： Jong-pil Son ,  Young-soo Sohn

    IPC分类号： G11C29/44

    CPC分类号： G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

    摘要： A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

    Memory device
    4.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US08929165B2

    公开(公告)日：2015-01-06

    申请号：US13611084

    申请日：2012-09-12

    申请人： Jong-pil Son ,  Young-soo Sohn

    发明人： Jong-pil Son ,  Young-soo Sohn

    IPC分类号： G11C8/00 ,  G11C11/408 ,  G11C29/04 ,  G11C29/00 ,  G11C16/08

    CPC分类号： G11C29/44 ,  G11C8/00 ,  G11C11/4087 ,  G11C16/08 ,  G11C17/16 ,  G11C29/04 ,  G11C29/787 ,  G11C29/808 ,  G11C2029/4402

    摘要： A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

    摘要翻译： 一种存储器件，包括：存储单元阵列，包括正常存储单元和排列成行和列的备用存储单元，所述备用存储单元包括包括常规存储单元的常规列和至少一个备用存储单元的备用列，段匹配确定电路， 段地址，其中行地址信息对应于故障段并产生负载控制信号;以及列匹配确定电路，配置为响应于具有列地址的负载控制信号将对应于故障列的列地址信息进行比较，并产生 列地址替换控制信号，其中响应于列地址替换控制信号，连接到故障段的故障列的存储器单元被连接到备用存储器单元的列的存储器单元替换。

    Memory device having page state informing function
    5.
    发明授权
    Memory device having page state informing function 有权

    公开(公告)号：US09627015B2

    公开(公告)日：2017-04-18

    申请号：US14852890

    申请日：2015-09-14

    申请人： Young-soo Sohn ,  Kwang-il Park ,  Sei-jin Kim ,  Tae-young Kim

    发明人： Young-soo Sohn ,  Kwang-il Park ,  Sei-jin Kim ,  Tae-young Kim

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/109 ,  G11C7/1063 ,  G11C2207/2272

    摘要： A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

    Integrated circuit devices using power supply circuits with feedback from a replica load
    6.
    发明授权
    Integrated circuit devices using power supply circuits with feedback from a replica load 有权
    使用具有来自复制负载的反馈的电源电路的集成电路器件

    公开(公告)号：US09059698B2

    公开(公告)日：2015-06-16

    申请号：US13240635

    申请日：2011-09-22

    申请人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

    发明人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

    IPC分类号： G05F1/00 ,  H03K19/003 ,  G05F1/575

    CPC分类号： H03K19/00361 ,  G05F1/575

    摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

    摘要翻译： 集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。 该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。 电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。 复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

    Integrated circuit memory devices having internal command generators therein that support extended command sets using independent and dependent commands
    7.
    发明授权
    Integrated circuit memory devices having internal command generators therein that support extended command sets using independent and dependent commands 有权
    其中具有内部命令发生器的集成电路存储器件支持使用独立和相关命令的扩展命令集

    公开(公告)号：US07817494B2

    公开(公告)日：2010-10-19

    申请号：US12236978

    申请日：2008-09-24

    申请人： Young-soo Sohn ,  Kwang-Il Park ,  Seung-Jun Bae

    发明人： Young-soo Sohn ,  Kwang-Il Park ,  Seung-Jun Bae

    IPC分类号： G11C11/00

    CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18

    摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.

    摘要翻译： 集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。 内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。 例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。 或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。 这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

    DATA PROCESSING DEVICE AND METHOD USING ERROR DETECTION CODE, METHOD OF COMPENSATING FOR DATA SKEW, AND SEMICONDUCTOR DEVICE HAVING THE DATA PROCESSING DEVICE
    8.
    发明申请
    DATA PROCESSING DEVICE AND METHOD USING ERROR DETECTION CODE, METHOD OF COMPENSATING FOR DATA SKEW, AND SEMICONDUCTOR DEVICE HAVING THE DATA PROCESSING DEVICE 有权
    数据处理装置和使用错误检测码的方法，数据处理装置的补偿方法和具有数据处理装置的半导体装置

    公开(公告)号：US20120117443A1

    公开(公告)日：2012-05-10

    申请号：US13239156

    申请日：2011-09-21

    申请人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

    发明人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

    IPC分类号： G06F11/08

    CPC分类号： H03M13/09 ,  H04L1/0061

    摘要： A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial.A data processing method for transmitting a first data includes a step of generating a first data, a step of generating cyclic redundancy check (CRC) information having at least one bit whose binary value is modified in response to a toggle information, and a step of generating a combined data by combining the generated CRC information and the first data as a combined data and outputting the combined data in serial.

    摘要翻译： 一种用于发送第一数据的数据处理装置包括被配置为提供第一数据的数据生成器，循环冗余校验（CRC）发生器，被配置为生成具有响应于切换信息修改其二进制值的至少一个比特的至少一个比特的CRC信息 以及数据发送器，被配置为组合CRC信息和第一数据作为组合数据，并串行输出组合数据。 用于发送第一数据的数据处理方法包括产生第一数据的步骤，产生具有响应于切换信息修改其二进制值的至少一个比特的循环冗余校验（CRC）信息的步骤，以及步骤 通过组合生成的CRC信息和第一数据作为组合数据来生成组合数据，并串行输出组合数据。

    Data processing device and method using error detection code, method of compensating for data skew, and semiconductor device having the data processing device
    10.
    发明授权
    Data processing device and method using error detection code, method of compensating for data skew, and semiconductor device having the data processing device 有权
    使用错误检测码的数据处理装置和方法，补偿数据偏移的方法，以及具有数据处理装置的半导体装置

    公开(公告)号：US08645790B2

    公开(公告)日：2014-02-04

    申请号：US13239156

    申请日：2011-09-21

    申请人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

    发明人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

    IPC分类号： H03M13/00

    CPC分类号： H03M13/09 ,  H04L1/0061

    摘要： A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial. A data processing method for transmitting a first data includes a step of generating a first data, a step of generating cyclic redundancy check (CRC) information having at least one bit whose binary value is modified in response to a toggle information, and a step of generating a combined data by combining the generated CRC information and the first data as a combined data and outputting the combined data in serial.

    摘要翻译： 一种用于发送第一数据的数据处理装置包括被配置为提供第一数据的数据生成器，循环冗余校验（CRC）发生器，被配置为生成具有响应于切换信息修改其二进制值的至少一个比特的至少一个比特的CRC信息 以及数据发送器，被配置为组合CRC信息和第一数据作为组合数据，并串行输出组合数据。 用于发送第一数据的数据处理方法包括产生第一数据的步骤，产生具有响应于切换信息修改其二进制值的至少一个比特的循环冗余校验（CRC）信息的步骤，以及步骤 通过组合生成的CRC信息和第一数据作为组合数据来生成组合数据，并串行输出组合数据。