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27 条记录 (耗时 0.016 秒)

    Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same
    1.
    发明授权
    Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same 有权
    用于在更宽的电源电压范围内产生稳定的升压电压的升压电压产生电路和具有该升压电压的半导体存储器件

    公开(公告)号：US07501881B2

    公开(公告)日：2009-03-10

    申请号：US11707001

    申请日：2007-02-16

    申请人： Jae Youn Youn ,  Han Na Park

    发明人： Jae Youn Youn ,  Han Na Park

    IPC分类号： G05F1/10

    CPC分类号： H02M3/1584 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08

    摘要： The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease. Accordingly, the boosting voltage generating circuit of example embodiments may generate a stable boosting voltage under a wider range of supply voltage.

    摘要翻译： 示例性实施例的升压电压产生电路可以包括升压电平检测单元，第一增压泵和第二增压泵。 升压电平检测单元可以被配置为产生目标电平检测信号和余量电平检测信号。 与目标电压电平相比，目标电平检测信号可以根据升压电压的电平具有逻辑状态，并且边沿电平检测信号可以根据升压电压的电平与余量电压电平相比具有逻辑状态 ，余量电压电平高于目标电压电平。 可以基于目标电压电平来控制第一增压泵。 可以基于余量电压电平来控制第二增压泵。 根据示例性实施例的升压电压产生电路，第二增压泵的升压电压的过冲可能显着降低。 因此，示例性实施例的升压电压产生电路可以在更宽的电源电压范围内产生稳定的升压电压。

    Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof
    2.
    发明授权
    Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof 失效

    公开(公告)号：US06842382B2

    公开(公告)日：2005-01-11

    申请号：US10217799

    申请日：2002-08-12

    申请人： Jae-Hoon Kim ,  Jae-Youn Youn

    发明人： Jae-Hoon Kim ,  Jae-Youn Youn

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C16/04

    CPC分类号： G11C5/14 ,  G11C11/413

    摘要： An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.

    Semiconductor memory device and method of controlling sense amplifier of semiconductor memory device
    5.
    发明授权
    Semiconductor memory device and method of controlling sense amplifier of semiconductor memory device 失效
    半导体存储器件及半导体存储器件读出放大器的控制方法

    公开(公告)号：US08194485B2

    公开(公告)日：2012-06-05

    申请号：US12552615

    申请日：2009-09-02

    申请人： Sang-Hoon Jung ,  Jae-Youn Youn ,  Young-Sun Min

    发明人： Sang-Hoon Jung ,  Jae-Youn Youn ,  Young-Sun Min

    IPC分类号： G11C7/02

    CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4091 ,  G11C2211/4065

    摘要： A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal.

    摘要翻译： 半导体存储器件包括至少一个读出放大器，控制器和读出放大器驱动器。 读出放大器包括PMOS读出放大器和NMOS读出放大器，其配置为分别响应于第一电源电压和第二电源电压被激活，并且检测和放大对应位线对之间的电压差。 控制器被配置为响应于外部命令来设置操作模式，以根据设定的操作模式控制PMOS驱动激活信号的激活定时和NMOS驱动激活信号，并且输出PMOS驱动激活信号和NMOS 驱动启动信号。 读出放大器驱动器被配置为分别响应于PMOS驱动激活信号和NMOS驱动器激活信号将第一和第二电源电压施加到PMOS和NMOS读出放大器。

    Device and method for performing a partial array refresh operation
    6.
    发明授权
    Device and method for performing a partial array refresh operation 有权
    用于执行部分阵列刷新操作的设备和方法

    公开(公告)号：US07426151B2

    公开(公告)日：2008-09-16

    申请号：US11459896

    申请日：2006-07-25

    申请人： Jae-Hoon Kim ,  Jae-Youn Youn

    发明人： Jae-Hoon Kim ,  Jae-Youn Youn

    IPC分类号： G11C11/406

    CPC分类号： G11C5/147 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622

    摘要： An internal voltage generator includes a control section and a switchable internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a partial array self refresh (PASR) signal. The internal voltage may be supplied to banks selected by the bank PASR signal, thereby enabling refresh operations in the entire bank, or an internal voltage adequate to partially enable refresh operations in all the banks may be supplied. Thus, unnecessary power consumption may be effectively controlled.

    摘要翻译： 内部电压发生器包括控制部分和可切换内部电压产生电路。 控制部分响应于存储体激活命令和用于使能存储体的存储体激活信号产生控制信号。 内部电压产生电路接收参考电压，并响应于控制信号输出等于参考电压的内部电压。 当组激活命令和存储体激活信号同时使能时，控制信号被使能。 响应于部分阵列自刷新（PASR）信号产生存储体激活信号。 可以将内部电压提供给由存储体PASR信号选择的存储体，从而使得能够在整个存储体中进行刷新操作，或者可以提供足以部分地实现所有存储体中的刷新操作的内部电压。 因此，可以有效地控制不必要的功率消耗。

    Semiconductor memory device and refresh method thereof
    8.
    发明授权
    Semiconductor memory device and refresh method thereof 有权
    半导体存储器件及其刷新方法

    公开(公告)号：US09076504B2

    公开(公告)日：2015-07-07

    申请号：US13661773

    申请日：2012-10-26

    申请人： Jong-Ho Lee ,  Kyu-Chang Kang ,  Hyo-Chang Kim ,  Jae-Youn Youn ,  Sang-Jae Rhee

    发明人： Jong-Ho Lee ,  Kyu-Chang Kang ,  Hyo-Chang Kim ,  Jae-Youn Youn ,  Sang-Jae Rhee

    IPC分类号： G11C7/08 ,  G11C11/406 ,  G11C11/4091

    CPC分类号： G11C7/08 ,  G11C11/40626 ,  G11C11/4091 ,  G11C2211/4065 ,  G11C2211/4068

    摘要： A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.

    摘要翻译： 半导体存储器件和半导体存储器件的自刷新方法。 半导体存储器件包括：包括一个或多个存储单元的存储单元阵列; 连接到感测线和互补感测线的感测放大器，以及感测/放大存储在所述一个或多个存储器单元中的数据; 以及读出放大器控制电路，其在刷新操作期间通过感测线路顺序地将具有不同电平的第一电压和第二电压提供给读出放大器。

    Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
    10.
    发明授权
    Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density 有权
    具有分离字线驱动电路的半导体存储器件具有提供增加的集成密度的布局图案

    公开(公告)号：US07729195B2

    公开(公告)日：2010-06-01

    申请号：US11935887

    申请日：2007-11-06

    申请人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

    发明人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14

    摘要： Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

    摘要翻译： 提供具有分层字线结构的半导体存储器件。 一块子字线驱动电路（SWDB）设置在第一存储器块和第二存储器块之间。 SWDB包括布置在多个SWD列中的多个子字线驱动器（SWD）电路，每个SWD列具有在第一和第二存储器块之间沿第一方向延伸的四个SWD电路。 两个相邻的SWD列包括用于驱动从SWD组沿着第一方向延伸到第一和第二存储块的多个子字线的SWD组。