公开(公告)号：US07482962B2

公开(公告)日：2009-01-27

申请号：US11778565

申请日：2007-07-16

申请人： Taejoong Song ,  Jongmin Park ,  Youngsik Hur ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

发明人： Taejoong Song ,  Jongmin Park ,  Youngsik Hur ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

IPC分类号： H03M1/66

CPC分类号： H04L27/0004

摘要： Embodiments of the invention may provide for digital wavelet generators utilized in providing flexible spectrum-sensing resolutions for a Multi-Resolution Spectrum Sensing (MRSS) technique. Embodiments of the invention may provide for either multi-point or multi-rate digital wavelet generators. These digital wavelet generators may utilizing the same hardware resource optimally, and the various wavelet bases may be generated by changing the memory addressing schemes or clock speeds.

摘要翻译： 本发明的实施例可以提供用于为多分辨率频谱感测（MRSS）技术提供灵活的频谱感测分辨率的数字小波发生器。 本发明的实施例可以提供多点或多速率数字小波发生器。 这些数字小波发生器可以最佳地利用相同的硬件资源，并且可以通过改变存储器寻址方案或时钟速度来生成各种小波基。

公开(公告)号：US20080024336A1

公开(公告)日：2008-01-31

申请号：US11778557

申请日：2007-07-16

申请人： Jongmin Park ,  Taejoong Song ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

发明人： Jongmin Park ,  Taejoong Song ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

IPC分类号： H03M1/00

CPC分类号： H04B17/382

摘要： Embodiments of the present invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may comprise of an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.

摘要翻译： 本发明的实施例可以提供用于认知无线电系统的频谱感测的长延迟发生器。 长延迟发生器可以包括模数转换器（ADC），存储器元件和数模转换器（DAC）。 存储器元件可以利用移位寄存器组或随机存取存储器（RAM）单元。 长延迟发生器可以通过数字化接收的信号，延迟数字域中的接收信号，并将延迟的信号重建为模拟来提供可选择的延迟。 然后可以使用模拟自相关技术将模拟延迟信号与原始输入信号进行比较或相关，以确定是否已识别或以其他方式检测到有意义的信号类型。

公开(公告)号：US20080034171A1

公开(公告)日：2008-02-07

申请号：US11778565

申请日：2007-07-16

申请人： Taejoong Song ,  Jongmin Park ,  Youngsik Hur ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

发明人： Taejoong Song ,  Jongmin Park ,  Youngsik Hur ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

IPC分类号： G06F12/00

CPC分类号： H04L27/0004

摘要： Embodiments of the invention may provide for digital wavelet generators utilized in providing flexible spectrum-sensing resolutions for a Multi-Resolution Spectrum Sensing (MRSS) technique. Embodiments of the invention may provide for either multi-point or multi-rate digital wavelet generators. These digital wavelet generators may utilizing the same hardware resource optimally, and the various wavelet bases may be generated by changing the memory addressing schemes or clock speeds.

摘要翻译： 本发明的实施例可以提供用于为多分辨率频谱感测（MRSS）技术提供灵活的频谱感测分辨率的数字小波发生器。 本发明的实施例可以提供多点或多速率数字小波发生器。 这些数字小波发生器可以最佳地利用相同的硬件资源，并且可以通过改变存储器寻址方案或时钟速度来生成各种小波基。

公开(公告)号：US07528751B2

公开(公告)日：2009-05-05

申请号：US11778557

申请日：2007-07-16

申请人： Jongmin Park ,  Taejoong Song ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

发明人： Jongmin Park ,  Taejoong Song ,  Kyutae Lim ,  Chang-Ho Lee ,  Jeongsuk Lee ,  Kihong Kim ,  Seongsoo Lee ,  Haksun Kim ,  Joy Laskar

IPC分类号： H03M1/00

CPC分类号： H04B17/382

摘要： Embodiments of the invention may provide for a long delay generator for the spectrum sensing of cognitive radio systems. The long delay generator may include an Analog-to-Digital Converter (ADC), memory element, and Digital-to-Analog Converter (DAC). The memory element may utilize shift register bank or Random-Access Memory (RAM) cells. The long delay generator may provide for a selectable delay by digitizing the received signal, delaying the received signal in the digital domain, and reconstructing the delayed signal as an analog. The analog delayed signal may then be compared or otherwise correlated with the original input signal using an analog auto-correlation technique to determine whether a meaningful signal type has been identified or otherwise detected.

摘要翻译： 本发明的实施例可以提供用于认知无线电系统的频谱感测的长延迟发生器。 长延迟发生器可以包括模数转换器（ADC），存储器元件和数模转换器（DAC）。 存储器元件可以利用移位寄存器组或随机存取存储器（RAM）单元。 长延迟发生器可以通过数字化接收的信号，延迟数字域中的接收信号，并将延迟的信号重建为模拟来提供可选择的延迟。 然后可以使用模拟自相关技术将模拟延迟信号与原始输入信号进行比较或相关，以确定是否已识别或以其他方式检测到有意义的信号类型。

公开(公告)号：US08334708B1

公开(公告)日：2012-12-18

申请号：US13194315

申请日：2011-07-29

申请人： Jeongwon Cha ,  Taejoong Song ,  Changhyuk Cho ,  Minsik Ahn ,  Chang-Ho Lee ,  Wangmyong Woo ,  Jae Joon Chang

发明人： Jeongwon Cha ,  Taejoong Song ,  Changhyuk Cho ,  Minsik Ahn ,  Chang-Ho Lee ,  Wangmyong Woo ,  Jae Joon Chang

IPC分类号： H03K19/00 ,  H03K19/02

CPC分类号： H03K19/0019

摘要： Example driver circuits can utilize shared-charge recycling charge pump structures. In particular, an example shared-charge recycling process may be applied to a clock buffer and charge transfer cells of the charge pump in a driver circuit. An example recycling process may include recycling of shared charges between the capacitors/capacitances in the charge transfer cells. An example recycling process may use the charges in one or more capacitors to charge one or more other capacitors before the charges are wasted or otherwise discharged to ground. Such recycling may significantly reduce the power consumption of the charge pump while still providing a high output voltage level, according to an example embodiment of the invention.

摘要翻译： 示例驱动电路可以利用共享电荷循环电荷泵结构。 特别地，示例性共享电荷回收过程可以应用于驱动器电路中的电荷泵的时钟缓冲器和电荷转移单元。 示例回收过程可以包括在电荷转移单元中的电容器/电容之间再循环共享电荷。 示例回收过程可以在一个或多个电容器中的电荷在电荷被浪费或以其它方式放电到地之前对一个或多个其它电容器充电。 根据本发明的示例性实施例，这种再循环可以显着降低电荷泵的功耗，同时仍然提供高输出电压电平。

公开(公告)号：US09652580B2

公开(公告)日：2017-05-16

申请号：US14709885

申请日：2015-05-12

申请人： Taejoong Song ,  Jae-Ho Park ,  Sanghoon Baek ,  Giyoung Yang ,  Sang-Kyu Oh ,  Hyosig Won

发明人： Taejoong Song ,  Jae-Ho Park ,  Sanghoon Baek ,  Giyoung Yang ,  Sang-Kyu Oh ,  Hyosig Won

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5072 ,  G06F2217/84

摘要： A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.

公开(公告)号：US09928333B2

公开(公告)日：2018-03-27

申请号：US15184227

申请日：2016-06-16

申请人： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

发明人： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC分类号： G06F17/5077 ,  H01L27/0207 ,  H01L27/11807

摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US09324619B2

公开(公告)日：2016-04-26

申请号：US14814601

申请日：2015-07-31

申请人： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

发明人： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

IPC分类号： H01L21/33 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/027 ,  H01L21/762 ,  H01L27/11 ,  H01L27/108

CPC分类号： H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

摘要： A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

摘要翻译： 制造在第一和第二区域之间具有第一区域，第二区域和第三区域的半导体器件的方法包括分别形成从第一和第二区域中的衬底突出的第一和第二预活性图案，形成掩模图案 将衬底上的第三区域曝光，使用掩模图案分别进行蚀刻掩模的第一蚀刻工艺，分别形成第一和第二有源图案，并在衬底上形成栅极结构。

公开(公告)号：US09564368B2

公开(公告)日：2017-02-07

申请号：US15077351

申请日：2016-03-22

申请人： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

发明人： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

IPC分类号： H01L27/088 ,  H01L21/70 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/027 ,  H01L21/762 ,  H01L27/11 ,  H01L27/108 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

摘要： A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

摘要翻译： 制造在第一和第二区域之间具有第一区域，第二区域和第三区域的半导体器件的方法包括分别形成从第一和第二区域中的衬底突出的第一和第二预活性图案，形成掩模图案 将衬底上的第三区域曝光，使用掩模图案分别进行蚀刻掩模的第一蚀刻工艺，分别形成第一和第二有源图案，并在衬底上形成栅极结构。