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    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY
    5.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY 有权
    方法，装置和能源节约系统，其中包括使用注册次级不间断电源改进处理器核心深度断电退出

    公开(公告)号：US20120166852A1

    公开(公告)日：2012-06-28

    申请号：US13335880

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev S. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Alon Naveh ,  Michael Zelikson ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

    摘要： Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

    摘要翻译： 本发明的实施例涉及从计算设备处理器核心深度掉电来改善退出等待时间。 处理器状态数据可以在深度掉电模式期间通过提供第二不间断电压供应来始终保持驻留在处理器的关键状态寄存器内的保持器电路。 当这些寄存器接收到指示处理器电源状态将从活动处理器电源状态降低到零处理器电源状态的控制信号时，它们将临界状态数据从临界状态寄存器锁存器写入到所提供的保持器电路 不间断的电源。 然后，当寄存器接收到指示处理器的处理器电源状态将增加回到活动处理器功率状态的控制信号时，存储在保持器电路中的临界状态数据被写回到临界状态寄存器锁存器。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE
    6.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE 有权
    能源效率和能源保护的方法，装置和系统，包括能源效率处理器使用深度掉电模式的热力

    公开(公告)号：US20120166839A1

    公开(公告)日：2012-06-28

    申请号：US13335831

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/32

    CPC分类号： G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/171

    摘要： Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

    摘要翻译： 本发明的实施例涉及使用零电压处理器状态的电子设备处理器的节能和节省热节流。 例如，处理器管芯可以包括功率控制单元（PCU）和具有电源门和热传感器的执行单元。 PCU连接到热传感器，以确定执行单元的温度是否已经增加到大于上限阈值，例如当执行单元处理处于活动处理器电源状态的数据时。 PCU也连接到电源门，因此在这种检测时，它可以将主处理器的电源状态改变到零处理器电源状态，以降低执行单元的温度。 当传感器检测到温度降低到低于下限阈值时，PCU可以将处理器电源状态改变回活动状态。

    MIGRATING THREADS BETWEEN ASYMMETRIC CORES IN A MULTIPLE CORE PROCESSOR
    8.
    发明申请
    MIGRATING THREADS BETWEEN ASYMMETRIC CORES IN A MULTIPLE CORE PROCESSOR 有权
    在多核心处理器之间的不对称线路之间的传输螺纹

    公开(公告)号：US20140026146A1

    公开(公告)日：2014-01-23

    申请号：US13995340

    申请日：2011-12-29

    申请人： Sanjeev S. Jahagirdar ,  Varghese George ,  Inder Sodhi

    发明人： Sanjeev S. Jahagirdar ,  Varghese George ,  Inder Sodhi

    IPC分类号： G06F9/50

    CPC分类号： G06F9/5083 ,  G06F9/30003 ,  G06F9/4856

    摘要： Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

    摘要翻译： 一些实现提供了将线程从处理器的第一核心迁移到处理器的第二核心的技术和布置。 例如，一些实现可以标识被安排在处理器处执行的一个或多个线程。 处理器可以包括多个核，包括具有第一特征的第一核和第二核具有与第一特性不同的第二特性。 可以启动由第一核心执行一个或多个线程。 可以确定是否应用迁移策略。 响应于确定应用迁移策略，可以启动一个或多个线程从第一核到第二核的迁移。

    Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode
    9.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode 有权
    节能和节能的方法，装置和系统，包括使用深度掉电模式的节能处理器热节流

    公开(公告)号：US09122464B2

    公开(公告)日：2015-09-01

    申请号：US13335831

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/00 ,  G06F1/20 ,  G06F1/32

    CPC分类号： G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/171

    摘要： Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

    摘要翻译： 本发明的实施例涉及使用零电压处理器状态的电子设备处理器的节能和节省热节流。 例如，处理器管芯可以包括功率控制单元（PCU）和具有电源门和热传感器的执行单元。 PCU连接到热传感器，以确定执行单元的温度是否已经增加到大于上限阈值，例如当执行单元处理处于活动处理器电源状态的数据时。 PCU也连接到电源门，因此在这种检测时，它可以将主处理器的电源状态改变到零处理器电源状态，以降低执行单元的温度。 当传感器检测到温度降低到低于下限阈值时，PCU可以将处理器电源状态改变回活动状态。

    CONFIGURABLE POWER SUPPLIES FOR DYNAMIC CURRENT SHARING
    10.
    发明申请
    CONFIGURABLE POWER SUPPLIES FOR DYNAMIC CURRENT SHARING 有权
    用于动态电流共享的可配置电源

    公开(公告)号：US20150177798A1

    公开(公告)日：2015-06-25

    申请号：US14138550

    申请日：2013-12-23

    申请人： Sandeep K. Venishetti ,  Sanjeev S. Jahagirdar ,  Srinivas Thota

    发明人： Sandeep K. Venishetti ,  Sanjeev S. Jahagirdar ,  Srinivas Thota

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26 ,  G06F1/189 ,  G06F1/263 ,  G06F1/3287 ,  H02J2003/001 ,  Y02D10/171 ,  Y10T307/352

    摘要： An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.

    摘要翻译： 一种设备包括分配网络，其包括被配置为从第一电压源接收第一功率的电路和来自第二电压源的第二功率，并且向多个电子电路模块（ECB）中的每一个发送功率，包括递送第一ECB 第一个欧洲央行的权力和第二个欧洲央行的第二个ECB的权力。 第一ECB功率包括第一功率的第一部分和第二功率的第一部分。 该装置还包括电源管理逻辑以动态地调整要提供给每个ECB的功率。 响应于第一ECB的第一活动级别的改变，电源管理逻辑是通过调整第一功率的第一部分并调整第二功率的第一部分来改变第一ECB功率。 描述和要求保护其他实施例。