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    Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module
    1.
    发明授权
    Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module 有权
    集成电路，对集成电路的存储单元阵列进行编程的方法以及存储器模块

    公开(公告)号：US07796449B2

    公开(公告)日：2010-09-14

    申请号：US12351023

    申请日：2009-01-09

    申请人： Josef Willer ,  Gert Koebernik

    发明人： Josef Willer ,  Gert Koebernik

    IPC分类号： G11C7/00

    CPC分类号： G11C16/22

    摘要： An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed.

    摘要翻译： 提供具有多个存储单元的存储单元布置的集成电路和存储单元布置控制器。 存储单元布置控制器被配置为使得在对多个存储器单元中的至少一个存储单元进行编程期间，驱动与被编程的存储器单元相邻布置的至少一个存储单元，以将存储单元屏蔽到 被编程。

    INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE
    2.
    发明申请
    INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE 有权
    集成电路，编程集成电路的存储单元阵列的方法和存储器模块

    公开(公告)号：US20090201740A1

    公开(公告)日：2009-08-13

    申请号：US12351023

    申请日：2009-01-09

    申请人： Josef WILLER ,  Gert Koebernik

    发明人： Josef WILLER ,  Gert Koebernik

    IPC分类号： G11C16/06 ,  G11C7/02 ,  G11C7/00 ,  G11C5/06

    CPC分类号： G11C16/22

    摘要： An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed.

    摘要翻译： 提供具有多个存储单元的存储单元布置的集成电路和存储单元布置控制器。 存储单元布置控制器被配置为使得在对多个存储器单元中的至少一个存储单元进行编程期间，驱动与被编程的存储器单元相邻布置的至少一个存储单元，以将存储单元屏蔽到 被编程。

    Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
    5.
    发明授权
    Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation 有权
    在访问操作中使用多个缓冲电路来操作该集成电路的集成电路和方法

    公开(公告)号：US07920430B2

    公开(公告)日：2011-04-05

    申请号：US12166112

    申请日：2008-07-01

    申请人： Gert Koebernik ,  Jan Gutsche ,  Christoph Friederich ,  Detlev Richter

    发明人： Gert Koebernik ,  Jan Gutsche ,  Christoph Friederich ,  Detlev Richter

    IPC分类号： G11C7/10

    CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括存储存储单元的多个多位信息，多个缓冲电路，每个缓冲电路耦合到多个位信息存储存储单元中的至少一个多位信息存储存储单元，以及一个 控制器，被配置为控制访问操作以使用耦合到要被访问的所述至少一个多位信息存储存储器单元的缓冲电路访问存储单元的至少一个多位信息，以及至少一个其他多位信息的缓冲电路 存储存储器单元耦合到至少一个其他多位信息存储存储单元。

    Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation
    8.
    发明申请
    Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation 有权
    在接入操作中使用多个缓冲电路的集成电路及其操作方法

    公开(公告)号：US20100002503A1

    公开(公告)日：2010-01-07

    申请号：US12166112

    申请日：2008-07-01

    申请人： Gert Koebernik ,  Jan Gutsche ,  Christoph Friederich ,  Detlev Richter

    发明人： Gert Koebernik ,  Jan Gutsche ,  Christoph Friederich ,  Detlev Richter

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C8/00

    CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括存储存储单元的多个多位信息，多个缓冲电路，每个缓冲电路耦合到多个位信息存储存储单元中的至少一个多位信息存储存储单元，以及一个 控制器，被配置为控制访问操作以使用耦合到要被访问的所述至少一个多位信息存储存储器单元的缓冲电路访问存储单元的至少一个多位信息，以及至少一个其他多位信息的缓冲电路 存储存储器单元耦合到至少一个其他多位信息存储存储单元。