公开(公告)号：US20120273884A1

公开(公告)日：2012-11-01

申请号：US13095690

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

摘要翻译： 功率器件包括半导体区域，该半导体区域又包括多个交替布置的第一和第二导电类型的柱。 第二导电类型的多个柱中的每一个还包括沿着第二导电类型的柱的深度彼此顶部布置的多个第二导电类型的注入区，以及填充有第二导电类型的半导体材料的沟槽部 在第二导电类型的多个植入区域的正上方。

公开(公告)号：US08836028B2

公开(公告)日：2014-09-16

申请号：US13095690

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/0878 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

摘要翻译： 在一般方面，功率器件可以包括设置在衬底上的至少一个N型外延层和在所述至少一个N型外延层中限定交替的P-N柱的多个N柱和P柱。 功率器件还可以包括有源区和端接区，其中终端区围绕有源区。 交替的P-N柱可以设置在有源区域和终止区域中，其中终止区域可以包括预定数量的浮动P柱。

公开(公告)号：US20120273916A1

公开(公告)日：2012-11-01

申请号：US13095652

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

IPC分类号： H01L29/872

CPC分类号： H01L29/0634 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US08928077B2

公开(公告)日：2015-01-06

申请号：US12234549

申请日：2008-09-19

申请人： JaeGil Lee ,  Chongman Yun ,  Hocheol Jang ,  Christopher L. Rexer ,  Praveen Muraleedharan Shenoy ,  Dwayne S. Reichl ,  Joseph A. Yedinak

发明人： JaeGil Lee ,  Chongman Yun ,  Hocheol Jang ,  Christopher L. Rexer ,  Praveen Muraleedharan Shenoy ,  Dwayne S. Reichl ,  Joseph A. Yedinak

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC分类号： H01L29/66712 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.

摘要翻译： 在一个一般方面，功率器件包括具有多个第一导电类型的柱的有源区，该多个柱交替地布置有多个第二导电类型的柱，其中有源区中的第二导电类型的多个柱各自具有 基本相同的宽度。 功率器件包括围绕有源区域的至少一部分的端接区域，并且具有多个第一导电类型的柱，其交替地布置有多个第二导电类型的支柱，其中第二导电类型的多个支柱 有源区域各自具有基本上相同的宽度，并且小于端接区域中的第二导电类型的柱的每个宽度。 功率器件包括设置在有源区和端接区之间的过渡区。

公开(公告)号：US07230313B2

公开(公告)日：2007-06-12

申请号：US10682323

申请日：2003-10-09

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Bernard J. Czeck ,  Douglas J. Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Bernard J. Czeck ,  Douglas J. Lange

IPC分类号： H01L29/78

CPC分类号： H01L29/405 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/7803

摘要： An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

摘要翻译： 集成电路包括具有器件层的管芯。 绝缘层设置在器件层上。 死街定义了模具的最外边界。 包括多个电阻元件的分压网络导出多个预定的偏置电压。 场板终端包括设置在氧化物层上并相对于彼此和相对于模具街道横向间隔开的多个场板。 多个场板中的每一个电连接到相应的偏置电压。 施加到给定场板的偏置电压由该场板相对于模具街道的接近度确定并随其增加。

公开(公告)号：US07118951B2

公开(公告)日：2006-10-10

申请号：US11130794

申请日：2005-05-17

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/7395

摘要： An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

公开(公告)号：US06906362B2

公开(公告)日：2005-06-14

申请号：US10315719

申请日：2002-12-10

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

IPC分类号： H01L29/739 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/7395

摘要： An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

公开(公告)号：US06798019B2

公开(公告)日：2004-09-28

申请号：US10055211

申请日：2002-01-23

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Jack E. Wojslawowicz ,  Bernard J. Czeck ,  Robert D. Baran ,  Douglas Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Jack E. Wojslawowicz ,  Bernard J. Czeck ,  Robert D. Baran ,  Douglas Lange

IPC分类号： H01L2973

CPC分类号： H01L29/0696 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/7395 ,  H01L29/7397

摘要： An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.

摘要翻译： IGBT具有沿着基带3的长度连续或分段的源极条2a，2b的条纹单元。相反的条由N +接触区域20周期性地连接在一起，以沿着源极条2a，2b的宽度提供沟道电阻 。 对于连续条纹，两个顺序接触区域20a，20b之间的电阻在中间是最大的，并且电流集中在源极接触区域20附近。触点20之间的间隔越宽，两个N +触点20之间的中点的电阻降低越大 。