公开(公告)号：US10985243B2

公开(公告)日：2021-04-20

申请号：US16992244

申请日：2020-08-13

申请人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

发明人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L23/29 ,  H01L23/31 ,  H01L29/15 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/778 ,  H01L29/66

摘要： A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

公开(公告)号：US10784341B2

公开(公告)日：2020-09-22

申请号：US16252952

申请日：2019-01-21

申请人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

发明人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L23/29 ,  H01L23/31 ,  H01L29/15 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/778 ,  H01L29/66

摘要： A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

公开(公告)号：US10084075B2

公开(公告)日：2018-09-25

申请号：US15624445

申请日：2017-06-15

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L21/3065 ,  H01L29/205 ,  H01L29/15

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

公开(公告)号：US10854600B2

公开(公告)日：2020-12-01

申请号：US16577629

申请日：2019-09-20

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L21/338 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

公开(公告)号：US09711615B2

公开(公告)日：2017-07-18

申请号：US15222039

申请日：2016-07-28

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/205 ,  H01L29/20

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

公开(公告)号：US10468406B2

公开(公告)日：2019-11-05

申请号：US14509750

申请日：2014-10-08

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/15 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.

公开(公告)号：US09419120B2

公开(公告)日：2016-08-16

申请号：US14533752

申请日：2014-11-05

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

摘要翻译： 提供了一种晶体管器件，其包括基底结构和覆盖在基底结构上的超晶格结构，并且包括具有倾斜侧壁的多通道脊。 多通道脊包括多个异质结构，每个异质结构形成多通道脊的通道，其中至少一个异质结构的参数相对于多个异质结构中的其它异质结构而变化。 晶体管器件还包括三边形栅极接触，其沿着其深度的至少一部分包围并基本上围绕多通道脊的顶部和侧面。

公开(公告)号：US09385224B2

公开(公告)日：2016-07-05

申请号：US14458906

申请日：2014-08-13

申请人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

发明人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

IPC分类号： H01L29/76 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/302 ,  H01L29/66

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

摘要翻译： 公开了一种集成电路，其包括具有在单通道器件区域中覆盖衬底结构的单个共享异质结构的第一部分的单通道器件，以及与单个共用异质结构的第一部分接触的栅极接触。 集成电路还包括多通道器件，其包括覆盖多通道器件区域中的衬底结构的单个共享异质结构的第二部分，覆盖在单个共用异质结构的第二部分上的阻挡层，以及覆盖在阻挡层上的超晶格结构， 超晶格结构包括多个异质结构。 单个共享异质结构中的隔离区域将单通道器件与多通道器件隔离。

公开(公告)号：US20160293713A1

公开(公告)日：2016-10-06

申请号：US14676285

申请日：2015-04-01

申请人： BETTINA A. NECHAY ,  Robert S. Howell ,  Eric J. Stewart ,  Howell George Henry ,  Justin Andrew Parke ,  Ronald G. Freitag

发明人： BETTINA A. NECHAY ,  Robert S. Howell ,  Eric J. Stewart ,  Howell George Henry ,  Justin Andrew Parke ,  Ronald G. Freitag

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/778 ,  H01L29/205 ,  H01L29/10 ,  H01L29/423 ,  H01L29/15 ,  H01L29/20

CPC分类号： H01L29/7783 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7851

摘要： A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.

摘要翻译： 提供了一种晶体管器件，其包括基底结构和覆盖在基底结构上的超晶格结构。 超晶格结构包括具有延伸到基部结构的侧面的多通道脊。 多通道脊包括多个异质结构，每个异质结构形成多通道脊的通道。 提供三面门配置，其围绕并基本上围绕多通道脊的顶部和侧面沿其深度的至少一部分包围。 三面栅极配置被配置为沿三面栅极配置重新分配峰值电场，以便于晶体管器件的击穿电压的增加。

公开(公告)号：US20140264273A1

公开(公告)日：2014-09-18

申请号：US13802747

申请日：2013-03-14

申请人： Robert S. Howell ,  Eric J. Stewart ,  Bettina A. Nechay ,  Justin A. Parke ,  Harlan C. Cramer ,  Jeffrey D. Hartman

发明人： Robert S. Howell ,  Eric J. Stewart ,  Bettina A. Nechay ,  Justin A. Parke ,  Harlan C. Cramer ,  Jeffrey D. Hartman

IPC分类号： H01L29/778 ,  H01L29/15

CPC分类号： H01L29/7784 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1037 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462

摘要： The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.

摘要翻译： 本发明涉及一种包括外延结构的器件，该外延结构包括具有最上面的2DxG通道，最下面的2DxG通道和位于最上面和最下面的2DxG通道之间的至少一个中间2DxG通道的超晶格结构，源极和漏极之间可操作地连接到每个 的2DxG通道，以及位于源极和漏极之间的多个沟槽。 每个沟槽具有限定第一侧壁，第二侧壁和位于其间的底部的长度，宽度和深度尺寸，每个沟槽的底部位于或最下面的2DxG通道。 栅极电极位于最上面的2DxG通道之上，栅电极位于每个沟槽内，使得栅电极的底表面与每个的第一侧壁表面，底表面和第二侧壁表面并置 的壕沟。