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    Method of welding thermocouples to silicon wafers for temperature monitoring in rapid thermal processing
    1.
    发明授权
    Method of welding thermocouples to silicon wafers for temperature monitoring in rapid thermal processing 失效
    将热电偶焊接到硅晶片的方法用于快速热处理中的温度监测

    公开(公告)号：US4787551A

    公开(公告)日：1988-11-29

    申请号：US46848

    申请日：1987-05-04

    申请人： Judy L. Hoyt ,  Kenneth E. Williams ,  James F. Gibbons

    发明人： Judy L. Hoyt ,  Kenneth E. Williams ,  James F. Gibbons

    IPC分类号： B23K9/00 ,  B23K15/00 ,  B23K35/30 ,  H01L21/66 ,  B23K31/02

    CPC分类号： B23K35/30 ,  B23K15/0046 ,  B23K9/0035 ,  H01L22/12 ,  H01L2924/0002

    摘要： Disclosed is a method of welding a temperature-sensing thermocouple to a silicon wafer for sensing the temperature of the wafer during rapid thermal processing using TIG welding and/or electron-beam welding. In one embodiment, a ball of silicon is formed on the bead at one end of a thermocouple by placing the thermocouple on a silicon chip and then melting the silicon chip with a TIG welder. The ball and thermocouple are then placed on the surface of a silicon wafer and the ball and surface are then melted whereby the ball of silicon flows into the silicon wafer. In placing the thermocouple on an edge portion of a silicon wafer, the wafer is supported on a tantalum plate with the edge portion of the wafer extending beyond the plate. A molybdenum sheet is positioned on the top surface of the wafer with the edge portion of the wafer exposed. A TIG arc is established with the molybdenum layer and then the arc is moved to the edge portion of the wafer for melting the silicon. In attaching the thermocouple on the silicon wafer other than on an edge portion, electron-beam welding is employed. An electron beam at low power is focused on the ball of silicon, and then the power of the electron beam is increased while the beam is pulsed so that the ball and adjacent silicon wafer are melted.

    摘要翻译： 公开了一种将温度感测热电偶焊接到硅晶片的方法，用于在使用TIG焊接和/或电子束焊接的快速热处理期间感测晶片的温度。 在一个实施例中，通过将热电偶放置在硅芯片上，然后用TIG焊机熔化硅芯片，在热电偶一端的珠上形成硅球。 然后将球和热电偶放置在硅晶片的表面上，然后熔化球和表面，由此硅球流入硅晶片。 在将热电偶放置在硅晶片的边缘部分上时，晶片被支撑在钽板上，晶片的边缘部分延伸超过该板。 钼片位于晶片的顶表面上，其晶片的边缘部分露出。 用钼层建立TIG弧，然后将电弧移动到晶片的边缘部分以熔化硅。 在将热电偶安装在除了边缘部分之外的硅晶片上时，采用电子束焊接。 低功率的电子束聚焦在硅球上，然后电子束的功率增加，而光束被脉冲，使得球和相邻的硅晶片熔化。

    Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x layer
    2.
    发明授权
    Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x layer 失效
    制造具有应变Si1-xGex层的半导体器件

    公开(公告)号：US5256550A

    公开(公告)日：1993-10-26

    申请号：US715054

    申请日：1991-06-12

    申请人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

    发明人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

    IPC分类号： H01L21/20 ,  H01L21/205

    CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/015 ,  Y10S438/902 ,  Y10S438/938

    摘要： The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.

    摘要翻译： 本发明包括一种在应变下使用至少一个异质外延层的器件和电路的制造方法。 基于先前已知的无盖层的平衡理论，异质外延层的厚度超过了在结晶衬底上的无盖异质外延层的计算的平衡临界厚度的两倍。 在异质外延层的生长之后，在高于异质外延层的生长温度的温度下处理该结构。 应变异质外延层（第二层）在第一底层晶体层的表面上外延生长，产生异质结。 随后，在第二应变异质外延层的主要暴露表面上沉积或生长第三晶体层。 第三晶体层的优选生长方式是外延生长。 第三结晶层的组成必须使得在沉积或生长时，第三层基本上连续地结合到第二层的异质外延结构。 在至少三层结构生长之后，在超过第二异质外延层的生长温度的温度下处理该结构。 第三结晶层的存在防止在第一晶体层衬底和第二异质外延层之间产生大量的失配位错。

    Gate electrode with depletion suppression and tunable workfunction
    3.
    发明授权
    Gate electrode with depletion suppression and tunable workfunction 有权
    具有耗尽抑制和可调功能的栅电极

    公开(公告)号：US07867859B1

    公开(公告)日：2011-01-11

    申请号：US12140955

    申请日：2008-06-17

    申请人： Steven Hung ,  Judy L. Hoyt ,  James F. Gibbons

    发明人： Steven Hung ,  Judy L. Hoyt ,  James F. Gibbons

    IPC分类号： H01L21/336 ,  H01L21/20 ,  H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L29/1054 ,  H01L21/28079 ,  H01L29/4958

    摘要： Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices. The ability to reduce gate depletion effects also provides enhanced device current drive.

    摘要翻译： 通过具有可调谐的有效功函数和减少的栅极耗尽效应的栅极结构来提高半导体器件的性能。 根据示例性实施例，半导体器件的设计阈值电压被调整为包括提供具有能够使半导体器件处于选定电压的功能的功能门的方式。 栅极形成为具有不同电功能的两种不同的导电材料，这两种导电材料都显着地有助于栅极的整体功能。 选择两种导电材料中的每一种的相对组成，厚度和布置，以获得不同于两层中的每一层的功函数的栅电极功函数，并设定半导体器件的阈值电压。 栅电极的有效功函数的可调性可应用于各种半导体器件。 降低栅极耗尽效应的能力还提供增强的器件电流驱动。

    Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film
    5.
    发明授权
    Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film 失效
    半导体处理与Si1-xGex薄膜上的硅帽

    公开(公告)号：US5084411A

    公开(公告)日：1992-01-28

    申请号：US277593

    申请日：1988-11-29

    申请人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

    发明人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

    IPC分类号： H01L21/20 ,  H01L21/205

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0262 ,  Y10S148/015 ,  Y10S438/902

    摘要： Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625.degree. and 825.degree. C.

    摘要翻译： 根据以下发现提供了具有硅到SiGe合金异质结的改进的器件。 使用X射线形貌和透射电子显微镜来定量由作为化学气相沉积技术的限制反应处理（LRP）形成的生长的Si1-xGex膜中的失配位错间隔。 这些分析技术也用于研究在通过LRP和分子束外延（MBE）生长的材料退火期间的位错形成。 失配位错首先出现在生长材料中的厚度对于两种生长技术是相似的。 在625℃至1000℃的范围内快速热退火后，还研究了封盖和未封装的膜的热稳定性。在含有外延硅帽的样品中观察到不合适的位错显着更少。 在625°和825℃之间的温度下退火未封层后，观察到在CVD和MBE膜中产生的失配位错数量的一些差异。

    Read only memory and integrated circuit and method of programming by laser means
    8.
    发明授权
    Read only memory and integrated circuit and method of programming by laser means 失效
    只读存储器和集成电路以及通过激光手段编程的方法

    公开(公告)号：US4233671A

    公开(公告)日：1980-11-11

    申请号：US1360

    申请日：1979-01-05

    申请人： Levy Gerzberg ,  Arnon Gat ,  Roger Melen ,  James F. Gibbons

    发明人： Levy Gerzberg ,  Arnon Gat ,  Roger Melen ,  James F. Gibbons

    IPC分类号： G11C17/06 ,  G11C17/08 ,  G11C17/14 ,  H01L21/268 ,  H01L21/8229 ,  H01L27/06 ,  H01L27/102 ,  H01L29/86

    CPC分类号： H01L27/0688 ,  G11C17/08 ,  G11C17/14 ,  H01L21/268

    摘要： A programmable read only memory (PROM) includes a first plurality of conductive lines, a second plurality of conductive lines and polycrystalline silicon material therebetween. At the crossing points of the first and second plurality of lines doped regions are provided in the polycrystalline silicon in contact with a second line and which extend at least partially through the material. To provide a diode interconnect at any crossing point, the associated region is irradiated by a laser beam to either cause diffusion of dopant atoms to the underlaying conductive line or activate implanted ions, thereby electrically interconnecting the first and second lines through a diode. The PROM is readily fabricated as part of a monolithic integrated circuit or electrical array and can be programmed after completion of the fabrication process.

    摘要翻译： 可编程只读存储器（PROM）包括第一多个导电线，第二多个导电线和它们之间的多晶硅材料。 在第一和第二多行线路掺杂区域的交叉点设置在与第二线路接触的多晶硅中，并且至少部分延伸通过该材料。 为了在任何交叉点提供二极管互连，相关联的区域被激光束照射以使掺杂剂原子扩散到底层导电线或激活注入离子，从而通过二极管电连接第一和第二线。 PROM易于制造为单片集成电路或电气阵列的一部分，并且可以在完成制造过程之后进行编程。

    Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam
    9.
    发明授权
    Method of forming polycrystalline semiconductor interconnections, resistors and contacts by applying radiation beam 失效
    通过施加辐射束形成多晶半导体互连，电阻和触点的方法

    公开(公告)号：US4214918A

    公开(公告)日：1980-07-29

    申请号：US950828

    申请日：1978-10-12

    申请人： Arnon Gat ,  Levy Gerzberg ,  James F. Gibbons

    发明人： Arnon Gat ,  Levy Gerzberg ,  James F. Gibbons

    IPC分类号： H01L21/268 ,  H01L21/321 ,  H01L21/263

    CPC分类号： H01L21/321 ,  H01L21/268 ,  Y10S148/093

    摘要： Low resistance, doped polycrystalline semiconductor connection patterns are fabricated by scanning a doped polycrystalline layer with a laser beam thereby increasing the crystal grain size, reducing defects in the grains, increasing charge carrier mobility and as a result reducing material resistivity. Semiconductor devices having increased circuit density and speed are realized through use of laser annealed polycrystalline semiconductor resistors, contacts and interconnections.

    摘要翻译： 通过用激光束扫描掺杂多晶层来制造低电阻，掺杂多晶半导体连接图案，从而增加晶粒尺寸，减少晶粒中的缺陷，增加电荷载流子迁移率，并因此降低材料电阻率。 具有增加的电路密度和速度的半导体器件通过使用激光退火的多晶半导体电阻器，触点和互连来实现。