公开(公告)号：US5430313A

公开(公告)日：1995-07-04

申请号：US220045

申请日：1994-03-30

申请人： Jumpei Kumagai ,  Tomohisa Mizuno

发明人： Jumpei Kumagai ,  Tomohisa Mizuno

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L23/00

CPC分类号： H01L27/088 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002

摘要： At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

摘要翻译： 在p型硅衬底的表面上形成n型源极/漏极扩散层。 在源极/漏极扩散层之间的衬底上形成由氧化硅膜形成的栅极绝缘膜，以与扩散层隔离。 在栅极绝缘膜上形成栅电极。 侧壁形成在栅极绝缘膜和栅电极的从基板向上延伸的侧面上。 在本发明中，侧壁由介电常数高于栅极绝缘膜（例如氮化硅膜）的材料构成。

公开(公告)号：US5302845A

公开(公告)日：1994-04-12

申请号：US121292

申请日：1993-09-15

申请人： Jumpei Kumagai ,  Tomohisa Mizuno

发明人： Jumpei Kumagai ,  Tomohisa Mizuno

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002

摘要： At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

摘要翻译： 在p型硅衬底的表面上形成n型源极/漏极扩散层。 在源极/漏极扩散层之间的衬底上形成由氧化硅膜形成的栅极绝缘膜，以与扩散层隔离。 在栅极绝缘膜上形成栅电极。 侧壁形成在栅极绝缘膜和栅电极的从基板向上延伸的侧面上。 在本发明中，侧壁由介电常数高于栅极绝缘膜（例如氮化硅膜）的材料构成。

公开(公告)号：US5561308A

公开(公告)日：1996-10-01

申请号：US366776

申请日：1994-12-30

申请人： Hideyuki Kamata ,  Jumpei Kumagai

发明人： Hideyuki Kamata ,  Jumpei Kumagai

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/10841 ,  H01L27/10864 ,  H01L29/78642 ,  Y10S257/906

摘要： A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first insulation film formed on the semiconductor substrate, a gate electrode and a second insulation film formed in sequence on the first insulation film, a trench being formed to extend through the second insulation film, the gate electrode and the first insulation film to an interior of the semiconductor substrate. A cylindrical gate insulation film is formed on a surface of the gate electrode which is exposed in the trench. A capacitor insulation film is formed on a surface of the semiconductor substrate exposed in the trench. A cylindrical conductive film is formed inside these insulation films. The cylindrical conductive film includes a region doped with an impurity of the first conductivity type and formed on a surface of the gate insulation film, a region doped with an impurity of a second conductivity type and formed on a surface of the second insulation film and a region doped with an impurity of the second conductivity type and formed on a surface of the capacitor insulation film. A conductive column is formed in a region surrounded by the cylindrical conductive film.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底上的第一绝缘膜，在第一绝缘膜上依次形成的栅电极和第二绝缘膜，形成为延伸穿过第二绝缘层的沟槽 膜，栅电极和第一绝缘膜到半导体衬底的内部。 在暴露在沟槽中的栅电极的表面上形成圆柱形栅极绝缘膜。 在暴露在沟槽中的半导体衬底的表面上形成电容器绝缘膜。 在这些绝缘膜内部形成圆柱状的导电膜。 圆柱形导电膜包括掺杂有第一导电类型的杂质并形成在栅极绝缘膜的表面上的区域，掺杂有第二导电类型的杂质并形成在第二绝缘膜的表面上的区域和 掺杂有第二导电类型的杂质并形成在电容器绝缘膜的表面上的区域。 导电柱形成在由圆柱形导电膜包围的区域中。

公开(公告)号：US5276343A

公开(公告)日：1994-01-04

申请号：US943144

申请日：1992-09-10

申请人： Jumpei Kumagai ,  Shizuo Sawada

发明人： Jumpei Kumagai ,  Shizuo Sawada

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10864 ,  H01L27/10823 ,  H01L27/10841

摘要： A DRAM cell having a bit line constituted by a semiconductor layer. The DRAM cell comprises a semiconductor substrate of a first conductivity type having a main surface, an insulating film formed on the main surface, an opening formed in the insulating film to communicate with the substrate, and a bit line formed by a semiconductor layer of a second conductivity type formed on the insulating film and that portion of the substrate which is exposed through the opening.

摘要翻译： 具有由半导体层构成的位线的DRAM单元。 DRAM单元包括具有主表面的第一导电类型的半导体衬底，在主表面上形成的绝缘膜，形成在绝缘膜中的与衬底连通的开口，以及由衬底的半导体层形成的位线 形成在绝缘膜上的第二导电类型和通过开口露出的基板的那部分。

公开(公告)号：US5194752A

公开(公告)日：1993-03-16

申请号：US813049

申请日：1991-12-23

申请人： Jumpei Kumagai ,  Shizuo Sawada

发明人： Jumpei Kumagai ,  Shizuo Sawada

IPC分类号： G11C11/4097 ,  H01L27/108

CPC分类号： G11C11/4097 ,  H01L27/10808

摘要： For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n pitch (n is natural numbers greater than or equal to 2).

摘要翻译： 为了增加包括动态存储单元阵列的半导体存储器件中的单元区域的图案密度，单元晶体管对的单元区域设置在半导体衬底中，以便与一个所需的位线和与其相邻的两个字线交叉， 并且单元区域的图案具有相同的方向。 用于将每个位线电连接到单元晶体管对的公共区域的触点在每个位线与单元区域相交的位置处以每个期望的间距提供在相应的位线上。 相邻位线的这些触点在位线方向依次移位约1 / 2n间距（n为大于或等于2的自然数）。

公开(公告)号：US4950617A

公开(公告)日：1990-08-21

申请号：US296307

申请日：1989-01-12

申请人： Jumpei Kumagai ,  Satoshi Shinozaki

发明人： Jumpei Kumagai ,  Satoshi Shinozaki

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/7836 ,  H01L27/0266 ,  H01L29/0847

摘要： This invention discloses a semiconductor integrated circuit in which an input protecting circuit and an inner circuit are formed on a single semiconductor substrate and a MOS transistor of the inner circuit is formed by mask-alignment. The source and drain regions of the MOS transistor of the input protecting circuit are formed by self-alignment, so that the impurity concentration of the source and drain regions is increased and the diffusion resistance thereof is reduced, thereby increasing the junction breakdown power caused by a drain current. In addition, the radii of curvature of the junction curved surface portions of the source and drain regions of the MOS transistor of the input protecting circuit are increased so as to reduce the electric field intensity at the junction curved surface portions, thereby improving the junction breakdown withstand characteristics.

公开(公告)号：US5041887A

公开(公告)日：1991-08-20

申请号：US522796

申请日：1990-05-14

申请人： Jumpei Kumagai ,  Shizuo Sawada

发明人： Jumpei Kumagai ,  Shizuo Sawada

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： In one-transistor.one-capacitor type dynamic memory cell, cell capacitor with a reduced junction leakage current comprises a MOS capacitor which is provided between a semiconductor substrate and a charge storage electrode disposed at a side wall of a trench through a first insulating film, and a stacked capacitor which is provided between the charge storage electrode and a capacitor plate electrode formed on a second insulating film covering the entire surface of the charge storage electrode. The equivalent silicon dioxide thickness of the first insulating film is thicker than that of the second insulating film, and the storage capacitance of the cell capacitor is rendered by a sum of the capacitance of the MOS capacitor and the capacitance of the stacked capacitor because these capacitors are electrically connected in parallel with each other.

公开(公告)号：US4941031A

公开(公告)日：1990-07-10

申请号：US416604

申请日：1989-10-03

申请人： Jumpei Kumagai ,  Syuso Fujii

发明人： Jumpei Kumagai ,  Syuso Fujii

IPC分类号： G11C11/401 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/0207 ,  G11C11/4097 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/922

摘要： A signal line runs in parallel with first to fourth bit lines on a memory cell array of a dynamic memory device. The signal line runs between and along the first and third bit lines, turns at a predetermined position, turns again and runs between and along the second and fourth bit lines. The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line and these bit lines are equal at about 1/2C.sub.F.

公开(公告)号：US5324975A

公开(公告)日：1994-06-28

申请号：US4303

申请日：1993-01-14

申请人： Jumpei Kumagai ,  Shizuo Sawada

发明人： Jumpei Kumagai ,  Shizuo Sawada

IPC分类号： G11C11/4097 ,  H01L27/108 ,  H01L23/48 ,  H01L29/40 ,  H01L29/44 ,  H01L29/52

CPC分类号： G11C11/4097 ,  H01L27/10808

摘要： For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n (n is natural numbers greater than or equal to 2) pitch.

摘要翻译： 为了增加包括动态存储单元阵列的半导体存储器件中的单元区域的图案密度，单元晶体管对的单元区域设置在半导体衬底中，以便与一个所需的位线和与其相邻的两个字线交叉， 并且单元区域的图案具有相同的方向。 用于将每个位线电连接到单元晶体管对的公共区域的触点在每个位线与单元区域相交的位置处以每个期望的间距提供在相应的位线上。 相邻位线的这些触点在位线方向依次移位约1 / 2n（n为大于或等于2的自然数）间距。

公开(公告)号：US5321300A

公开(公告)日：1994-06-14

申请号：US865681

申请日：1992-04-08

申请人： Yoshio Usuda ,  Hiroaki Itaba ,  Jumpei Kumagai ,  Seiji Kaki

发明人： Yoshio Usuda ,  Hiroaki Itaba ,  Jumpei Kumagai ,  Seiji Kaki

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： In a laser-broken fuse used in a memory redundancy technique, an aluminum wiring layer is formed on an interlevel insulating film. A portion of the wiring layer is selected to be broken to shut off conduction of the layer. A polysilicon-made heat member is provided in the interlevel insulating film at the place which is underneath the selected portion. The heat member is located on a field insulating film. This heat member generates heat by absorbing energy from a laser beam, and thermal-explodes in a sealed atmosphere so as to break the selected portion.

摘要翻译： 在存储器冗余技术中使用的激光断开熔丝中，在层间绝缘膜上形成铝布线层。 选择布线层的一部分被破坏以切断该层的传导。 在选择部分的下方的位置，在层间绝缘膜上设置多晶硅制成的加热部件。 加热构件位于场绝缘膜上。 该加热构件通过从激光束吸收能量而产生热量，并且在密封的气氛中热爆，从而破坏所选择的部分。