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24 条记录 (耗时 0.02 秒)

    Transistor with an offset gate structure
    1.
    发明授权
    Transistor with an offset gate structure 失效
    具有偏移栅极结构的晶体管

    公开(公告)号：US5430313A

    公开(公告)日：1995-07-04

    申请号：US220045

    申请日：1994-03-30

    申请人： Jumpei Kumagai ,  Tomohisa Mizuno

    发明人： Jumpei Kumagai ,  Tomohisa Mizuno

    IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L23/00

    CPC分类号： H01L27/088 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002

    摘要： At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

    摘要翻译： 在p型硅衬底的表面上形成n型源极/漏极扩散层。 在源极/漏极扩散层之间的衬底上形成由氧化硅膜形成的栅极绝缘膜，以与扩散层隔离。 在栅极绝缘膜上形成栅电极。 侧壁形成在栅极绝缘膜和栅电极的从基板向上延伸的侧面上。 在本发明中，侧壁由介电常数高于栅极绝缘膜（例如氮化硅膜）的材料构成。

    Transistor with an offset gate structure
    2.
    发明授权
    Transistor with an offset gate structure 失效
    具有偏移栅极结构的晶体管

    公开(公告)号：US5302845A

    公开(公告)日：1994-04-12

    申请号：US121292

    申请日：1993-09-15

    申请人： Jumpei Kumagai ,  Tomohisa Mizuno

    发明人： Jumpei Kumagai ,  Tomohisa Mizuno

    IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L27/088 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002

    摘要： At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

    摘要翻译： 在p型硅衬底的表面上形成n型源极/漏极扩散层。 在源极/漏极扩散层之间的衬底上形成由氧化硅膜形成的栅极绝缘膜，以与扩散层隔离。 在栅极绝缘膜上形成栅电极。 侧壁形成在栅极绝缘膜和栅电极的从基板向上延伸的侧面上。 在本发明中，侧壁由介电常数高于栅极绝缘膜（例如氮化硅膜）的材料构成。

    METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE 有权
    形成半导体器件结构和半导体器件的方法

    公开(公告)号：US20120168818A1

    公开(公告)日：2012-07-05

    申请号：US13412296

    申请日：2012-03-05

    申请人： Tomohisa Mizuno

    发明人： Tomohisa Mizuno

    IPC分类号： H01L29/165 ,  H01L21/336

    CPC分类号： H01L29/78654 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

    摘要： Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).

    摘要翻译： 公开了一种提高半导体元件的性能的方法和具有改进的性能的半导体元件。 形成半导体元件结构的方法包括异质结形成步骤，其中在其中保持应变状态的应变半导体层（21）和松弛半导体层（23,25）之间形成异质结。 通过从衬底（50）的表面进行离子注入而形成异质结，衬底（50）具有在绝缘氧化膜（40）上部分被覆盖层（30）覆盖的应变半导体层（20），并且改变应变半导体层 （20），其中通过缓和应变半导体层（20）的应变状态，在保持应变半导体层（21）的应变状态的同时，不会从覆盖层（30）向松弛的半导体层（23,25） ），其中存在与覆盖层（30）的屏蔽。