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    Semiconductor memory device having a bit line constituted by a semiconductor layer
    1.
    发明授权
    Semiconductor memory device having a bit line constituted by a semiconductor layer 失效
    具有由半导体层构成的位线的半导体存储器件

    公开(公告)号：US5276343A

    公开(公告)日：1994-01-04

    申请号：US943144

    申请日：1992-09-10

    申请人： Jumpei Kumagai ,  Shizuo Sawada

    发明人： Jumpei Kumagai ,  Shizuo Sawada

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10864 ,  H01L27/10823 ,  H01L27/10841

    摘要： A DRAM cell having a bit line constituted by a semiconductor layer. The DRAM cell comprises a semiconductor substrate of a first conductivity type having a main surface, an insulating film formed on the main surface, an opening formed in the insulating film to communicate with the substrate, and a bit line formed by a semiconductor layer of a second conductivity type formed on the insulating film and that portion of the substrate which is exposed through the opening.

    摘要翻译： 具有由半导体层构成的位线的DRAM单元。 DRAM单元包括具有主表面的第一导电类型的半导体衬底，在主表面上形成的绝缘膜，形成在绝缘膜中的与衬底连通的开口，以及由衬底的半导体层形成的位线 形成在绝缘膜上的第二导电类型和通过开口露出的基板的那部分。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5194752A

    公开(公告)日：1993-03-16

    申请号：US813049

    申请日：1991-12-23

    申请人： Jumpei Kumagai ,  Shizuo Sawada

    发明人： Jumpei Kumagai ,  Shizuo Sawada

    IPC分类号： G11C11/4097 ,  H01L27/108

    CPC分类号： G11C11/4097 ,  H01L27/10808

    摘要： For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n pitch (n is natural numbers greater than or equal to 2).

    摘要翻译： 为了增加包括动态存储单元阵列的半导体存储器件中的单元区域的图案密度，单元晶体管对的单元区域设置在半导体衬底中，以便与一个所需的位线和与其相邻的两个字线交叉， 并且单元区域的图案具有相同的方向。 用于将每个位线电连接到单元晶体管对的公共区域的触点在每个位线与单元区域相交的位置处以每个期望的间距提供在相应的位线上。 相邻位线的这些触点在位线方向依次移位约1 / 2n间距（n为大于或等于2的自然数）。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5324975A

    公开(公告)日：1994-06-28

    申请号：US4303

    申请日：1993-01-14

    申请人： Jumpei Kumagai ,  Shizuo Sawada

    发明人： Jumpei Kumagai ,  Shizuo Sawada

    IPC分类号： G11C11/4097 ,  H01L27/108 ,  H01L23/48 ,  H01L29/40 ,  H01L29/44 ,  H01L29/52

    CPC分类号： G11C11/4097 ,  H01L27/10808

    摘要： For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n (n is natural numbers greater than or equal to 2) pitch.

    摘要翻译： 为了增加包括动态存储单元阵列的半导体存储器件中的单元区域的图案密度，单元晶体管对的单元区域设置在半导体衬底中，以便与一个所需的位线和与其相邻的两个字线交叉， 并且单元区域的图案具有相同的方向。 用于将每个位线电连接到单元晶体管对的公共区域的触点在每个位线与单元区域相交的位置处以每个期望的间距提供在相应的位线上。 相邻位线的这些触点在位线方向依次移位约1 / 2n（n为大于或等于2的自然数）间距。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5041887A

    公开(公告)日：1991-08-20

    申请号：US522796

    申请日：1990-05-14

    申请人： Jumpei Kumagai ,  Shizuo Sawada

    发明人： Jumpei Kumagai ,  Shizuo Sawada

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10829

    摘要： In one-transistor.one-capacitor type dynamic memory cell, cell capacitor with a reduced junction leakage current comprises a MOS capacitor which is provided between a semiconductor substrate and a charge storage electrode disposed at a side wall of a trench through a first insulating film, and a stacked capacitor which is provided between the charge storage electrode and a capacitor plate electrode formed on a second insulating film covering the entire surface of the charge storage electrode. The equivalent silicon dioxide thickness of the first insulating film is thicker than that of the second insulating film, and the storage capacitance of the cell capacitor is rendered by a sum of the capacitance of the MOS capacitor and the capacitance of the stacked capacitor because these capacitors are electrically connected in parallel with each other.

    Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof
    6.
    发明授权
    Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof 失效
    具有堆叠电容器结构的半导体存储器件及其制造方法

    公开(公告)号：US4951175A

    公开(公告)日：1990-08-21

    申请号：US353765

    申请日：1989-05-18

    申请人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

    发明人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10808 ,  H01L27/10835

    摘要： A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor. After a capacitor insulation layer is formed on the second polycrystalline silicon layer, a third polycrystalline silicon layer is formed on the capacitor insulation layer so as to bury a recess of the second polycrystalline silicon layer. The third silicon layer constitutes the upper electrode of the capacitor.

    摘要翻译： 公开了一种具有层叠电容器单元结构的动态随机存取存储器，其具有设置在硅衬底上并具有MOSFET和电容器的存储单元。 在基板上形成绝缘层，在该绝缘层上形成第一多晶硅层。 这些层同时进行蚀刻并限定穿透它们的接触孔以与源的表面接触。 在第一多晶硅层上形成第二多晶硅层，以均匀地覆盖接触孔的内壁和通过接触孔露出的源的表面部分。 第一和第二硅层同时进行图案化以提供电容器的下电极。 在第二多晶硅层上形成电容器绝缘层之后，在电容器绝缘层上形成第三多晶硅层，从而埋入第二多晶硅层的凹部。 第三硅层构成电容器的上电极。

    Semiconductor memory device having a stacked capacitor cell structure
    9.
    发明授权
    Semiconductor memory device having a stacked capacitor cell structure 失效
    具有叠层电容器单元结构的半导体存储器件

    公开(公告)号：US5142639A

    公开(公告)日：1992-08-25

    申请号：US701884

    申请日：1991-05-17

    申请人： Yusuke Kohyama ,  Shizuo Sawada ,  Toshiharu Watanabe ,  Kinuyo Kohyama

    发明人： Yusuke Kohyama ,  Shizuo Sawada ,  Toshiharu Watanabe ,  Kinuyo Kohyama

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92

    CPC分类号： H01L27/10817 ,  H01L28/87

    摘要： In a stacked capacitor cell structure of a semiconductor memory device, the MIM (metal-insulator-metal) capacitor to be used as a transfer gate comprises at least a unit stack of a first insulation film, a lower capacitor electrode, a capacitor gate insulation film, an upper capacitor electrode, another capacitor gate insulation film and an extension of the lower capacitor electrode. Thus, the surface area of the lower capacitor electrode can be enlarged without increasing the plane area exclusively occupied by memory cells. Moreover, with such a configuration, since the surface area of the lower capacitor electrode can be augmented without increasing the film thickness of the electrode, the technical difficulties that the currently known methods of manufacturing semiconductor memory devices with a stacked capacitor cell structure encounter are effectively eliminated and consequently troubles such as short-circuited lower capacitor electrodes become non-existent.

    摘要翻译： 在半导体存储器件的叠层电容器单元结构中，用作转移栅的MIM（金属 - 绝缘体 - 金属）电容器至少包括第一绝缘膜，下电容器电极，电容器栅绝缘 薄膜，上电容器电极，另一电容器栅绝缘膜和下电容器电极的延伸。 因此，可以扩大下电容器电极的表面积而不增加由存储单元专门占用的面积。 此外，通过这样的结构，由于可以增加下电容电极的表面积而不增加电极的膜厚度，所以当前已知的制造具有层叠电容器单元结构的半导体存储器件的制造方法遇到的技术难度有效地 消除并且因此诸如短路的较低电容器电极的故障不再存在。

    Method of forming a contact hole in semiconductor integrated circuit
    10.
    发明授权
    Method of forming a contact hole in semiconductor integrated circuit 失效
    在半导体集成电路中形成接触孔的方法

    公开(公告)号：US5032528A

    公开(公告)日：1991-07-16

    申请号：US538764

    申请日：1990-06-15

    申请人： Yoshiaki Asao ,  Shizuo Sawada

    发明人： Yoshiaki Asao ,  Shizuo Sawada

    IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768

    CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/76802

    摘要： Regions having different impurity concentrations are formed in the main surface region of the semiconductor substrate. Accordingly, when the substrate is oxidized, oxide films having different thickness are formed. More specifically, the oxide film is formed more deeply on the surface region of the substrate having a high impurity concentration in which ions are injected than on the surface region in which no ions are injected. In the etching step, since the thinner oxide film is removed while the thicker oxide film remains, the surface of the region under the thinner oxide film is exposed, and thus a contact hole is formed. If, in the step of forming a contact hole, a portion of the thinner oxide film is covered by a resist pattern, only the regiion of the oxide film which is not masked by the resist pattern is etched and the substrate surface thereunder is exposed, and thus a contact hole is formed.