公开(公告)号：US5093282A

公开(公告)日：1992-03-03

申请号：US648311

申请日：1991-01-29

申请人： Jun-ichi Ohno ,  Koh-ichi Fukazawa ,  Masamichi Shindo

发明人： Jun-ichi Ohno ,  Koh-ichi Fukazawa ,  Masamichi Shindo

IPC分类号： H01L23/12 ,  D21H27/02 ,  D21H27/20 ,  H01L23/02 ,  H01L23/04 ,  H01L23/057 ,  H01L23/14 ,  H01L23/36 ,  H01L23/50

CPC分类号： H01L23/36 ,  H01L23/057 ,  H01L23/142 ,  H01L2224/32188 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  Y10T29/4913

摘要： Disclosed is a method for making a semiconductor device in which the Pin Grid Array (PGA) is improved so that a plurality of lead pins project from the undersurface of a metal base of a package substrate as input and output terminals of a Large Scale Integrated-circuit (LSI). The method comprises mounting a semiconductor chip on a heat sink to the base, superposing a printed circuit board on the base and connecting electrical lead pins to the outer ends of wiring patterns which are formed radially and downwardly projecting through the base, and assembling a metal shell to the upper surface of the base and covering the chip, bonding wires and wiring patterns, wherein the patterns are formed such that the outer ends of the patterns are located within the vicinity over the outermost rows and columns of through holes for connecting lead pins. Furthermore, in the method of producing the device, a central portion patterning wiring layer, which is electrically short-circuited for gold plating, is provided in order to stabilize the connection with the bonding wires, and this center layer is cut off after the short circuit is performed.

公开(公告)号：US5025347A

公开(公告)日：1991-06-18

申请号：US336429

申请日：1989-04-11

申请人： Masamichi Shindo ,  Toshiharu Sakurai ,  Hideo Taguchi ,  Nobu Izawa

发明人： Masamichi Shindo ,  Toshiharu Sakurai ,  Hideo Taguchi ,  Nobu Izawa

IPC分类号： H01L23/12 ,  H01L23/04 ,  H01L23/045 ,  H01L23/373

CPC分类号： H01L23/045 ,  H01L23/3731 ,  H01L23/3736 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152

摘要： A semiconductor device of a type having a pin grid array, comprises a printed circuit board and a planar metal stem with a plurality of through holes. The stem is made of metal having a coefficient of thermal expansion .alpha.s. The printed circuit board has a predetermined wiring pattern on its upper surface and is made of a material having a maximum coefficient .alpha.p in the widthwise direction. The printed circuit board is superposed over the upper surface of the metal stem. A plurality of lead pins have upper portions inserted into the through holes of the stem and board and are in alignment with each other when the board and the stem are superposed one upon another. Connecting members connect the upper portions of the lead pins with their corresponding wiring patterns. In the semiconductor device, the absolute value .DELTA..alpha. of the difference between the maximum coefficient .alpha.p of the board and the coefficient .alpha.s of the stem (.DELTA..alpha.=.alpha.p -.alpha.s) is less than or equal to "1.52.times.10.sup.-4 /L" (.DELTA..alpha..ltoreq.1.52 .times.10.sup.-4 /L).

摘要翻译： 具有针格阵列的类型的半导体器件包括印刷电路板和具有多个通孔的平面金属杆。 杆由具有热膨胀系数αs的金属制成。 印刷电路板在其上表面上具有预定的布线图案，并且由在宽度方向上具有最大系数αp的材料制成。 印刷电路板重叠在金属杆的上表面上。 多个引导销具有插入到杆和板的通孔中的上部，并且当板和杆彼此叠置时彼此对准。 连接构件将引脚的上部与其对应的布线图案相连。 在半导体器件中，板的最大系数αp与茎的系数αs之差（DELTAα=αp-αs）的绝对值DELTAα小于或等于“1.52×10 -3” 4 / L“（DELTAα

公开(公告)号：US5096081A

公开(公告)日：1992-03-17

申请号：US313555

申请日：1989-02-22

申请人： Masamichi Shindo ,  Toshiharu Sakurai ,  Hideo Taguchi ,  Nobu Izawa

发明人： Masamichi Shindo ,  Toshiharu Sakurai ,  Hideo Taguchi ,  Nobu Izawa

IPC分类号： H01L23/02 ,  H01L23/04

CPC分类号： H01L23/04 ,  H01L2924/0002

摘要： A metal cover plate for covering a semiconductor chip mounted on a package base plate comprises an upper central portion, a flange extending outwardly from outer edges of the central portion, and a side wall portion extending perpendicularly from the flange along all sides thereof. The central portion has at least one portion in parallel with the package base plate. The central portion is formed with reinforcing portions in the form ridges of gable roofs and valleys in cross section, formed along diagonal lines of the central portion or in the form of a ridge or rib substantially semicircular in cross section extending upwardly or downwardly along each diagonal line. Deflection of the top wall portion of the package during pressure application is thus be minimized.

公开(公告)号：US4874956A

公开(公告)日：1989-10-17

申请号：US177412

申请日：1988-04-04

申请人： Toshihiro Kato ,  Masamichi Shindo ,  Yoshihito Fukasawa

发明人： Toshihiro Kato ,  Masamichi Shindo ,  Yoshihito Fukasawa

IPC分类号： H01L21/66 ,  G01N21/88 ,  G01N21/956 ,  G01R31/265 ,  G01R31/28 ,  H01L21/60

CPC分类号： H01L24/85 ,  G01N21/88 ,  G01R31/2656 ,  G01R31/2853 ,  H01L24/78 ,  G01N2201/103 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/78 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181

摘要： An apparatus and a method for inspecting semiconductor devices, where a focused laser beam scans the semiconductor device, and the reflected beam thereof indicating height information of the reflection positions on the semiconductor device is detected for producing detected signals. The detected signals are compared with predetermined acceptance levels of height and distance.

摘要翻译： 检测半导体器件的装置和方法，其中聚焦的激光束扫描半导体器件，并且检测其表示半导体器件上的反射位置的高度信息的反射光束，以产生检测信号。 将检测到的信号与高度和距离的预定接受水平进行比较。