公开(公告)号：US07081651B2

公开(公告)日：2006-07-25

申请号：US10186153

申请日：2002-06-27

申请人： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

发明人： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

摘要翻译： 非易失性存储器件包括顺序层叠的隧道氧化物层，电荷存储层，阻挡绝缘层和栅电极，以及栅电极两侧的有源区中的杂质扩散层。 栅电极跨越形成在半导体衬底的预定区域中的器件隔离层之间的有源区，并且电荷存储层的边缘延伸成具有从栅电极突出的突出部分。 为了形成具有突出部分的电荷存储层，在形成在衬底中的器件隔离层之间的有源区域中形成包括第一至第三绝缘层的叠层绝缘层。 在堆叠绝缘层上形成与激活区交叉的多个栅电极，并且在栅电极的两个侧壁上形成侧墙。 使用侧壁间隔物和栅电极，对叠层绝缘层进行蚀刻以形成从栅电极的侧壁突出的电荷存储层。

公开(公告)号：US08629489B2

公开(公告)日：2014-01-14

申请号：US13357350

申请日：2012-01-24

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/76

CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

公开(公告)号：US20110079838A1

公开(公告)日：2011-04-07

申请号：US12961678

申请日：2010-12-07

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

公开(公告)号：US07864582B2

公开(公告)日：2011-01-04

申请号：US12191434

申请日：2008-08-14

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

公开(公告)号：US20100327371A1

公开(公告)日：2010-12-30

申请号：US12805962

申请日：2010-08-26

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US20090230451A1

公开(公告)日：2009-09-17

申请号：US12382385

申请日：2009-03-16

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/1083

摘要： A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.

摘要翻译： 半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线 其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。

公开(公告)号：US20090212340A1

公开(公告)日：2009-08-27

申请号：US12392656

申请日：2009-02-25

申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/11521

摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.

摘要翻译： 一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸 其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

公开(公告)号：US20090001451A1

公开(公告)日：2009-01-01

申请号：US12146653

申请日：2008-06-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

公开(公告)号：US20080246073A1

公开(公告)日：2008-10-09

申请号：US12138712

申请日：2008-06-13

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/00

CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US07400009B2

公开(公告)日：2008-07-15

申请号：US11043485

申请日：2005-01-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L21/28291 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11568 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/42332 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/792

摘要： Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.

摘要翻译： 提供浮动阱非易失性存储器件和方法。 存储器件包括半导体衬底和相邻的栅电极。 在基板和栅电极之间可以是具有第一介电常数的隧道绝缘层，具有大于第一介电常数的第二介电常数的阻挡绝缘层和电荷存储层。