公开(公告)号：US07081651B2

公开(公告)日：2006-07-25

申请号：US10186153

申请日：2002-06-27

申请人： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

发明人： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

摘要翻译： 非易失性存储器件包括顺序层叠的隧道氧化物层，电荷存储层，阻挡绝缘层和栅电极，以及栅电极两侧的有源区中的杂质扩散层。 栅电极跨越形成在半导体衬底的预定区域中的器件隔离层之间的有源区，并且电荷存储层的边缘延伸成具有从栅电极突出的突出部分。 为了形成具有突出部分的电荷存储层，在形成在衬底中的器件隔离层之间的有源区域中形成包括第一至第三绝缘层的叠层绝缘层。 在堆叠绝缘层上形成与激活区交叉的多个栅电极，并且在栅电极的两个侧壁上形成侧墙。 使用侧壁间隔物和栅电极，对叠层绝缘层进行蚀刻以形成从栅电极的侧壁突出的电荷存储层。

公开(公告)号：US06979628B2

公开(公告)日：2005-12-27

申请号：US10726788

申请日：2003-12-02

申请人： Hong-Soo Kim ,  Kyu-Charn Park ,  Jung-Dal Choi ,  Seong-Soon Cho

发明人： Hong-Soo Kim ,  Kyu-Charn Park ,  Jung-Dal Choi ,  Seong-Soon Cho

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76232 ,  H01L21/76237

摘要： Semiconductor devices and methods of forming devices that have field oxides in trenches are disclosed. According to the methods, a semiconductor substrate is prepared. An upper trench is formed at a predetermined region of the semiconductor substrate and a bottom trench is formed at a bottom surface of the upper trench. A field oxide is formed to fill the bottom trench and the upper trench. At this time, the upper trench has a wider width than the bottom trench.

摘要翻译： 公开了在沟槽中形成具有场氧化物的器件的半导体器件和方法。 根据该方法制备半导体衬底。 在半导体衬底的预定区域处形成上沟槽，并且在上沟槽的底表面处形成底沟槽。 形成场氧化物以填充底部沟槽和上部沟槽。 此时，上沟槽的宽度比底沟宽。

公开(公告)号：US07508048B2

公开(公告)日：2009-03-24

申请号：US10758802

申请日：2004-01-15

申请人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

发明人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

摘要翻译： 提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。 该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。 初始高压栅绝缘层形成为比焊垫绝缘层厚。 形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层 形成衬底以限定第二区域中的第二有源区。 然后去除焊盘绝缘层以露出第一有源区。 在暴露的第一有源区上形成低压栅极绝缘层。 因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域 。

公开(公告)号：US09257572B2

公开(公告)日：2016-02-09

申请号：US13844337

申请日：2013-03-15

申请人： Kwang-Soo Seol ,  Seong-Soon Cho

发明人： Kwang-Soo Seol ,  Seong-Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.

公开(公告)号：US08642438B2

公开(公告)日：2014-02-04

申请号：US13324035

申请日：2011-12-13

申请人： Young-Ho Lee ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

发明人： Young-Ho Lee ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

IPC分类号： H01L21/20 ,  H01L21/00

CPC分类号： H01L27/0629 ,  H01L27/11531 ,  H01L28/20

摘要： In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

摘要翻译： 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

公开(公告)号：US20120045901A1

公开(公告)日：2012-02-23

申请号：US13212349

申请日：2011-08-18

申请人： JONG-HYUK KIM ,  Keon-Soo Kim ,  Kwang-Shik Shin ,  Hyun-Chul Back ,  Seong-Soon Cho ,  Young-Bae Yoon ,  Jung-Hwan Park

发明人： JONG-HYUK KIM ,  Keon-Soo Kim ,  Kwang-Shik Shin ,  Hyun-Chul Back ,  Seong-Soon Cho ,  Young-Bae Yoon ,  Jung-Hwan Park

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816

摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

摘要翻译： 在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而改善对准边缘 。 掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。 与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

公开(公告)号：US07339242B2

公开(公告)日：2008-03-04

申请号：US11360112

申请日：2006-02-22

申请人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

发明人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

摘要翻译： 在一个实施例中，存储器件包括具有单元有源区和外围有源区的半导体衬底。 包括位线接触插头，公共源极线，外围栅极互连接触插头和外围金属互连接触插头的插头通过相同的工艺由相同的导电层形成。 此外，包括位线，电池金属互连，外围栅极互连和直接连接到插塞的外围金属互连的金属互连可以通过相同的工艺由相同的金属层形成。 因此，诸如插头和金属互连之类的互连结构被简化，因此它们的形成过程被简化。

公开(公告)号：US20160247818A1

公开(公告)日：2016-08-25

申请号：US15144863

申请日：2016-05-03

申请人： Kwang-Soo Seol ,  Seong-Soon Cho

发明人： Kwang-Soo Seol ,  Seong-Soon Cho

IPC分类号： H01L27/115 ,  H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  G11C16/10 ,  G11C16/26

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.

公开(公告)号：US20060186485A1

公开(公告)日：2006-08-24

申请号：US11360112

申请日：2006-02-22

申请人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

发明人： Seong-Soon Cho ,  Keon-Soo Kim ,  Jeong-Hyuk Choi ,  Sang-Youn Jo

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

摘要翻译： 在一个实施例中，存储器件包括具有单元有源区和外围有源区的半导体衬底。 包括位线接触插头，公共源极线，外围栅极互连接触插头和外围金属互连接触插头的插头通过相同的工艺由相同的导电层形成。 此外，包括位线，电池金属互连，外围栅极互连和直接连接到插塞的外围金属互连的金属互连可以通过相同的工艺由相同的金属层形成。 因此，诸如插头和金属互连之类的互连结构被简化，因此它们的形成过程被简化。

公开(公告)号：US06593188B2

公开(公告)日：2003-07-15

申请号：US09957816

申请日：2001-09-20

申请人： Seong-Soon Cho

发明人： Seong-Soon Cho

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

摘要： A non-volatile memory device and a fabrication method thereof are provided. A first polysilicon layer, an inter-gate dielectric layer, a second polysilicon layer and a capping layer are stacked sequentially. A first opening is formed through the inter-gate dielectric layer, the second polysilicon layer and the capping layer, thereby exposing the first polysilicon layer. A second opening is formed through the capping layer, thereby exposing the second polysilicon layer. On the resultant structure, a metal layer is formed and then thermally treated. As a result a metal silicide layer can be formed on the exposed portion of the first polysilicon layer and the exposed portion of the second polysilicon layer.