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公开(公告)号：US20170110509A1
公开(公告)日：2017-04-20
申请号：US15293771
申请日：2016-10-14
申请人： Jung-Hoon BAK , Woo-Jin KIM , Mina LEE , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Jung-Hoon BAK , Woo-Jin KIM , Mina LEE , Gwan-Hyeob KOH , Yoon-Jong SONG
CPC分类号： H01L27/228 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.
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公开(公告)号：US20180012933A1
公开(公告)日：2018-01-11
申请号：US15712130
申请日：2017-09-21
申请人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
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3.发明申请公开(公告)号：US20170069684A1
公开(公告)日：2017-03-09
申请号：US15157403
申请日：2016-05-17
申请人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
摘要翻译： 制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。 通过蚀刻停止层和第一绝缘中间层形成下电极。 在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。 通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。 第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。
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公开(公告)号：US20170069832A1
公开(公告)日：2017-03-09
申请号：US15186420
申请日：2016-06-17
申请人： Yong-Jae KIM , Woo-Jin KIM , Ki-Seok SUH , Shin-Hee HAN , Gwan-Hyeob KOH
发明人： Yong-Jae KIM , Woo-Jin KIM , Ki-Seok SUH , Shin-Hee HAN , Gwan-Hyeob KOH
CPC分类号： H01L43/08 , H01L27/228 , H01L43/12
摘要： A magnetoresistive memory device includes a lower electrode on a substrate, a magnetic tunnel junction (MTJ) structure on the lower electrode, and a mask structure. The MTJ structure includes a lower magnetic pattern, a tunnel barrier pattern, and an upper magnetic pattern which are stacked. The mask structure includes an upper electrode and a sidewall capping pattern enclosing a sidewall of the upper electrode.
摘要翻译： 磁阻存储器件包括衬底上的下电极，下电极上的磁隧道结（MTJ）结构和掩模结构。 MTJ结构包括堆叠的较低磁性图案，隧道势垒图案和上部磁性图案。 掩模结构包括上电极和封闭上电极的侧壁的侧壁封盖图案。
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公开(公告)号：US20180342669A1
公开(公告)日：2018-11-29
申请号：US15856256
申请日：2017-12-28
申请人： Dae-Shik KIM , Jeong-Heon PARK , Gwan-Hyeob KOH
发明人： Dae-Shik KIM , Jeong-Heon PARK , Gwan-Hyeob KOH
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228 , H01L29/41791 , H01L43/02 , H01L43/08
摘要： In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
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公开(公告)号：US20170345475A1
公开(公告)日：2017-11-30
申请号：US15402231
申请日：2017-01-09
申请人： Choong-Jae LEE , Gwan-Hyeob KOH , Bo-Young SEO , Yong-Kyu LEE
发明人： Choong-Jae LEE , Gwan-Hyeob KOH , Bo-Young SEO , Yong-Kyu LEE
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/005 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/22 , G11C13/0002
摘要： A resistive-type memory device is disclosed. The resistive-type memory device includes a memory cell array and a control logic circuit. The control logic circuit accesses the memory cell array in response to a command and an address provided from an outside. The memory cell array includes at least a first group of resistive-type memory cells and a second group of resistive-type memory cells. Each of the first group of resistive-type memory cells has a first feature size and each of the second group of resistive-type memory cells has a second feature size that is different from the first feature size.
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公开(公告)号：US20170271580A1
公开(公告)日：2017-09-21
申请号：US15418250
申请日：2017-01-27
申请人： Il-Mok PARK , Dae-Hwan KANG , Gwan-Hyeob KOH
发明人： Il-Mok PARK , Dae-Hwan KANG , Gwan-Hyeob KOH
CPC分类号： H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2427 , H01L27/2481 , H01L43/02 , H01L43/08 , H01L43/10 , H01L45/1233 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： Disclosed are a semiconductor memory device and a method of manufacturing the same. A first conductive line extends in a first direction on a substrate and has a plurality of protrusions and recesses that are alternately formed thereon. A second conductive line is arranged over the first conductive line in a second direction such that the first and the second conductive lines cross at the protrusions. A plurality of memory cell structures is positioned on the protrusions of the first conductive line and is contact with the second conductive line. A thermal insulating plug is positioned on the recesses of the first conductive line and reduces heat transfer between a pair of the neighboring cell structures in the first direction. Accordingly, the heat cross talk is reduced between the neighboring cell structures along the conductive line.
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公开(公告)号：US20170237000A1
公开(公告)日：2017-08-17
申请号：US15346751
申请日：2016-11-09
申请人： Masayuki TERAI , Dae-Hwan KANG , Gwan-Hyeob KOH
发明人： Masayuki TERAI , Dae-Hwan KANG , Gwan-Hyeob KOH
IPC分类号： H01L45/00
摘要： A variable resistance memory device and a method of manufacturing the same, the device including first conductive lines disposed in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to a top surface of the substrate; second conductive lines disposed in the second direction over the first conductive lines, each of the second conductive lines extending in the first direction; a memory unit between the first and second conductive lines, the memory unit being in each area overlapping the first and second conductive lines in a third direction substantially perpendicular to the top surface of the substrate, and the memory unit including a variable resistance pattern; and an insulation layer structure between the first and second conductive lines, the insulation layer structure covering the memory unit and including an air gap in at least a portion of an area overlapping neither the first conductive lines nor the second conductive lines in the third direction.
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