公开(公告)号：US07294577B2

公开(公告)日：2007-11-13

申请号：US11088984

申请日：2005-03-24

申请人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

发明人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

IPC分类号： H01L21/311

CPC分类号： H01L21/02052 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

摘要： There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

摘要翻译： 提供了一种制造半导体器件的方法，包括从其上具有氧化膜的半导体表面除去有机物质，半导体表面形成为具有50nm或更小的线宽度; 从半导体表面去除氧化膜; 干燥半导体表面而不使用有机溶剂; 以及在半导体表面干燥之后在半导体表面上形成硅化物层。

公开(公告)号：US20050215003A1

公开(公告)日：2005-09-29

申请号：US11088984

申请日：2005-03-24

申请人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

发明人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/02052 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

摘要： There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

摘要翻译： 提供了一种制造半导体器件的方法，包括从其上具有氧化膜的半导体表面除去有机物质，半导体表面形成为具有50nm或更小的线宽度; 从半导体表面去除氧化膜; 干燥半导体表面而不使用有机溶剂; 以及在半导体表面干燥之后在半导体表面上形成硅化物层。

公开(公告)号：US07030026B2

公开(公告)日：2006-04-18

申请号：US10695874

申请日：2003-10-30

申请人： Yuka Hayami ,  Junji Oh ,  Takashi Saiki ,  Masataka Kase

发明人： Yuka Hayami ,  Junji Oh ,  Takashi Saiki ,  Masataka Kase

IPC分类号： H01L21/302

CPC分类号： H01L21/31133 ,  H01L21/31138 ,  H01L21/823814 ,  H01L29/665

摘要： The semiconductor device fabrication method comprises the step of forming electrodes 20 in a first element region 14n and in a second element region 14p; the step of forming a first resist film 22 which is opened in the first element region 14n; the step of forming a first dopant diffused region 28 with the first resist film 22 and the gate electrode 20 as a mask; the first ashing processing step of ashing the first resist film 22; the step of forming a sidewall insulation film 42 over the side wall of the gate electrode 20; the step of forming a second resist film 44 which is opened in the first element region 14n; the forming a second dopant diffused region 48 with the second resist film 44, the gate electrode 20 and the sidewall insulation film 42 as a mask; and the second ashing processing step for ashing the second resist film 44. The ashing processing period of time in the first ashing processing step is shorter than the ashing processing period of time in the second ashing processing step.

摘要翻译： 半导体器件制造方法包括在第一元件区域14n和第二元件区域14p中形成电极20的步骤; 形成在第一元件区域14n中打开的第一抗蚀剂膜22的步骤; 以第一抗蚀剂膜22和栅电极20为掩模形成第一掺杂剂扩散区域28的步骤; 灰化第一抗蚀剂膜22的第一灰化处理步骤; 在栅电极20的侧壁上形成侧壁绝缘膜42的步骤; 形成在第一元件区域14n中打开的第二抗蚀剂膜44的步骤; 以第二抗蚀剂膜44，栅极电极20和侧壁绝缘膜42为掩模形成第二掺杂剂扩散区域48; 以及用于灰化第二抗蚀剂膜44的第二灰化处理步骤。 第一灰化处理步骤中的灰化处理时间段比第二灰化处理步骤中的灰化处理时间段短。

公开(公告)号：US20120009752A1

公开(公告)日：2012-01-12

申请号：US13238336

申请日：2011-09-21

申请人： Takayuki Wada ,  Masanori Terahara ,  Junji Oh

发明人： Takayuki Wada ,  Masanori Terahara ,  Junji Oh

IPC分类号： H01L21/336

CPC分类号： H01L21/76224 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

摘要翻译： 一种制造半导体器件的方法包括：形成具有第一表面和第二表面的硅衬底，所述硅衬底不包括氧化膜或厚度不大于100nm的氧化物膜，至少在第二表面上形成第一氧化膜 所述硅衬底通过至少覆盖所述第一表面形成第一膜，通过使所述第一膜图案化​​而在所述第一表面上形成掩模图案，通过使用所述掩模图案作为掩模在所述第一表面上形成器件分离区域，形成 在所述第一表面上形成栅极绝缘膜，经由所述栅极绝缘膜在所述第一表面上形成栅电极，在所述栅电极的每一侧上形成源极和漏极，以及在所述硅衬底上形成布线层，同时保持所述第一 氧化膜在第二表面上。

公开(公告)号：US08273630B2

公开(公告)日：2012-09-25

申请号：US13238336

申请日：2011-09-21

申请人： Takayuki Wada ,  Masanori Terahara ,  Junji Oh

发明人： Takayuki Wada ,  Masanori Terahara ,  Junji Oh

IPC分类号： H01L21/761

CPC分类号： H01L21/76224 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

摘要翻译： 一种制造半导体器件的方法包括：形成具有第一表面和第二表面的硅衬底，所述硅衬底不包括氧化膜或厚度不大于100nm的氧化物膜，至少在第二表面上形成第一氧化膜 所述硅衬底通过至少覆盖所述第一表面形成第一膜，通过使所述第一膜图案化​​而在所述第一表面上形成掩模图案，通过使用所述掩模图案作为掩模在所述第一表面上形成器件分离区域，形成 在所述第一表面上形成栅极绝缘膜，经由所述栅极绝缘膜在所述第一表面上形成栅电极，在所述栅电极的每一侧上形成源极和漏极，以及在所述硅衬底上形成布线层，同时保持所述第一 氧化膜在第二表面上。

公开(公告)号：US20120083082A1

公开(公告)日：2012-04-05

申请号：US13177337

申请日：2011-07-06

申请人： Kazushi Fujita ,  Junji Oh

发明人： Kazushi Fujita ,  Junji Oh

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成作为对准标记的沟槽，形成将区域暴露为器件隔离区域的掩模膜，并通过与上述对准标记对准来覆盖作为器件区域的区域 形成有沟槽的半导体衬底，以掩模膜为掩膜，各向异性蚀刻半导体衬底，以在该半导体衬底的器件隔离区域中形成器件隔离沟槽，并通过绝缘材料掩埋器件隔离沟槽 膜形成器件隔离绝缘膜。 在形成沟槽时，沟槽的形成深度小于与掩模膜的厚度相当的深度。

公开(公告)号：US20120083079A1

公开(公告)日：2012-04-05

申请号：US13176052

申请日：2011-07-05

申请人： Junji Oh

发明人： Junji Oh

IPC分类号： H01L21/336

CPC分类号： H01L29/105 ,  H01L21/3221 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/6659 ,  H01L29/7833

摘要： The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.

摘要翻译： 制造半导体器件的方法包括通过离子注入使半导体衬底的第一区域和第二区域非晶化，分别在第一区域和第二区域中注入第一杂质和第二杂质，激活注入的杂质以形成 第一杂质层和第二杂质层，在形成有杂质层的半导体衬底之上外延生长半导体层，在第一区域和第二区域上方生长栅极绝缘膜，以及在栅极绝缘膜上方形成第一栅电极 在第二区域中的第一区域和栅极绝缘膜上方的第二栅极电极。

公开(公告)号：US08043917B2

公开(公告)日：2011-10-25

申请号：US12468265

申请日：2009-05-19

申请人： Takayuki Wada ,  Masanori Terahara ,  Junji Oh

发明人： Takayuki Wada ,  Masanori Terahara ,  Junji Oh

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

摘要翻译： 一种制造半导体器件的方法包括：形成具有第一表面和第二表面的硅衬底，所述硅衬底不包括氧化膜或厚度不大于100nm的氧化物膜，至少在第二表面上形成第一氧化膜 所述硅衬底通过至少覆盖所述第一表面形成第一膜，通过使所述第一膜图案化​​而在所述第一表面上形成掩模图案，通过使用所述掩模图案作为掩模在所述第一表面上形成器件分离区域，形成 在所述第一表面上形成栅极绝缘膜，经由所述栅极绝缘膜在所述第一表面上形成栅电极，在所述栅电极的每一侧上形成源极和漏极，以及在所述硅衬底上形成布线层，同时保持所述第一 氧化膜在第二表面上。

公开(公告)号：US08294217B2

公开(公告)日：2012-10-23

申请号：US13172224

申请日：2011-06-29

申请人： Taiji Ema ,  Kazushi Fujita ,  Junji Oh

发明人： Taiji Ema ,  Kazushi Fujita ,  Junji Oh

IPC分类号： H01L21/70

CPC分类号： H01L21/823418 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/761 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.

摘要翻译： 半导体器件包括：第一晶体管，包括含有硼或磷的第一杂质层;形成在第一杂质层上方的第一外延层;形成在第一外延层上方的第一栅电极，其间形成有第一栅极绝缘膜， 漏区，以及包含含有硼和碳或砷或锑的第二杂质层的第二晶体管，形成在第二杂质层上方的第二外延层，形成在第二外延层上方的第二栅电极，第二栅极绝缘膜更薄 比其间形成的第一栅极绝缘膜，以及第二源极/漏极区域。

公开(公告)号：US08778786B1

公开(公告)日：2014-07-15

申请号：US13482394

申请日：2012-05-29

申请人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

发明人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

IPC分类号： H01L21/425 ,  H01L21/336 ,  H01L21/266 ,  H01L21/311

CPC分类号： H01L21/266 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/8239 ,  H01L27/0928

摘要： Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

摘要翻译： 在晶体管器件元件制造期间在衬底中防止硅损失是通过在制造过程中限制光刻胶掩模和化学氧化物层剥离的机会来实现的。 这可以通过使用在形成和剥离用于将植入区域识别到衬底中的光致抗蚀剂掩模保留在衬底上的保护层来实现。 此外，由于光致抗蚀剂掩模未对准而导致的不期望的返工步骤被消除，或者在器件元件制造过程中不会对来自衬底的硅消耗产生影响。 以这种方式，具有相同操作特性和性能的装置元件可以从批量到大量一致地进行。