公开(公告)号：US20110231734A1

公开(公告)日：2011-09-22

申请号：US13152962

申请日：2011-06-03

申请人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Hiroki Matsudaira

发明人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Hiroki Matsudaira

IPC分类号： G06F11/16

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/1072 ,  G11C16/06 ,  G11C29/52 ,  G11C29/78 ,  G11C2029/0411

摘要： A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.

摘要翻译： 存储器系统包括控制单元，其被配置为控制第一和第二存储器之间的数据传输。 控制单元执行复制处理，在将第二存储器的第一页中存储的数据读出到第一存储器之后，将数据写入第二存储器的第二页，在执行复制处理时确定纠错 从第一页读出的数据的处理成功，当纠错处理成功时存储第一存储器中的校正数据并将修正数据写入第二页，并且当纠错处理失败时读出 ，从第一页到第一存储器的数据，并将未经过纠错处理的数据写入第二页。

公开(公告)号：US20090222617A1

公开(公告)日：2009-09-03

申请号：US12394875

申请日：2009-02-27

申请人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/00 ,  G06F12/12 ,  G06F12/02

CPC分类号： G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/073 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/22 ,  G06F2212/7202 ,  G11C29/88 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

摘要翻译： 存储器系统包括：易失性第一存储单元，以预定单元管理数据的非易失性第二存储单元;以及控制器，其经由第一存储单元将主机设备请求的数据写入第二存储单元，并读出数据 由主机从第二存储单元请求到第一存储单元，并将数据传送到主机设备。 控制器包括管理表，用于管理出现在第二存储单元中的预定单元中的故障区域的数量，并且根据故障区域的数量，切换从主机设备向第二存储单元写入数据的操作模式 。

公开(公告)号：US20090222629A1

公开(公告)日：2009-09-03

申请号：US12394692

申请日：2009-02-27

申请人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0868 ,  G06F12/0862 ,  G06F2212/214

摘要： A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.

摘要翻译： 一种存储器系统，包括一个控制器，其读出写入到非易失性第二存储区域中的数据，从该数据读出数据被写入页单元，将第一存储区域写入作为包含在半导体存储器中的高速缓冲存储器 并将数据传送到主机设备。 当从主机设备的读出请求满足预定条件时，控制器执行从读出请求指定的逻辑地址范围的终端到第一存储区数据的第一预取中的至少一个， 当前处理到在页面单元中对齐的逻辑地址的边界，以及第二预取，用于从在页面单元中对齐的逻辑地址的边界读出数据到逻辑地址的下一个边界。

公开(公告)号：US20120124330A1

公开(公告)日：2012-05-17

申请号：US13358763

申请日：2012-01-26

申请人： Junji YANO ,  Kosuke HATSUDA ,  Hidenori MATSUZAKI

发明人： Junji YANO ,  Kosuke HATSUDA ,  Hidenori MATSUZAKI

IPC分类号： G06F12/06

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7211

摘要： A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.

摘要翻译： 根据本发明的实施例的存储器系统包括：数据管理单元120被划分为DR​​AM层管理单元120a，逻辑NAND层管理单元120b和物理NAND层管理单元120c至 使用各个管理单元独立地执行DRAM层，逻辑NAND层和物理NAND层的管理，从而执行有效的块管理。

公开(公告)号：US20090222636A1

公开(公告)日：2009-09-03

申请号：US12394870

申请日：2009-02-27

申请人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/02 ,  G06F15/177

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/7202

摘要： A memory system includes a controller that writes internal information concerning an operation state of the memory system in a special LBA area allocated to a predetermined logical address range in a second storing memory and writes the internal information in a first storing memory, and reads out, when the memory system is started up, the internal information to manage the operation state. The controller stores the internal information written in the first storing memory in the second storing memory as a snapshot when a predetermined condition is satisfied and, when an error occurs and the internal information written in the special LBA area cannot be read out when the memory system is started up, captures the internal information stored as the snapshot into the first storing memory and reads out the internal information.

摘要翻译： 存储器系统包括控制器，该控制器将关于存储器系统的操作状态的内部信息写入分配给第二存储存储器中的预定逻辑地址范围的特殊LBA区域中，并将内部信息写入第一存储存储器， 当内存系统启动时，内部信息管理操作状态。 当满足预定条件时，控制器将写入第一存储存储器中的第一存储存储器的内部信息作为快照存储，并且当存在错误发生并且当存储器系统中写入特殊LBA区域中的内部信息不能被读出时， 启动时，将存储为快照的内部信息捕获到第一个存储存储器中，并读出内部信息。

公开(公告)号：US20120239992A1

公开(公告)日：2012-09-20

申请号：US13486718

申请日：2012-06-01

申请人： Toshikatsu HIDA ,  Shinichi KANNO ,  Hirokuni YANO ,  Kazuya KITSUNAI ,  Shigehiro ASANO ,  Junji YANO

发明人： Toshikatsu HIDA ,  Shinichi KANNO ,  Hirokuni YANO ,  Kazuya KITSUNAI ,  Shigehiro ASANO ,  Junji YANO

IPC分类号： G11C29/00 ,  G06F11/16

CPC分类号： G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

摘要翻译： 一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定 。 该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。 该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。