公开(公告)号：US20170278857A1

公开(公告)日：2017-09-28

申请号：US15263832

申请日：2016-09-13

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shinya ARAI

IPC: H01L27/115 ,  G11C16/26 ,  G11C16/04 ,  H01L21/28

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L21/28282 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11568 ,  H01L28/00

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US20150221667A1

公开(公告)日：2015-08-06

申请号：US14614588

申请日：2015-02-05

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor memory device according to one embodiment includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract translation: 根据一个实施例的半导体存储器件包括具有半导体材料，第一电极膜，第一绝缘膜，堆叠体和三个或更多个半导体柱的连接构件。 层叠体包括交替堆叠的第二电极膜和第二绝缘膜。 半导体柱沿着两个或更多个方向排列，沿层叠方向延伸，穿过层叠体和第一绝缘膜，并连接到连接构件。 该装置包括设置在半导体柱和层叠体之间以及连接构件和第一电极膜之间的第三绝缘膜。 至少在一个第二电极膜和第三绝缘膜之间设置电荷存储层。

公开(公告)号：US20160240552A1

公开(公告)日：2016-08-18

申请号：US14729161

申请日：2015-06-03

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shinya ARAI

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a conductive layer provided on the substrate; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a coupling portion provided in the conductive layer; a semiconductor portion provided integrally in the stacked body and in the coupling portion; a charge storage film provided between the semiconductor portion and the plurality of electrode layers; and an interconnect portion provided integrally in the stacked body and in the conductive layer and extending in a stacking direction of the stacked body. The interconnect portion includes a side surface provided in the conductive layer, and the side surface is in contact with an entire side surface of the semiconductor portion in the coupling portion.

Abstract translation: 根据一个实施例，半导体存储器件包括衬底; 设置在基板上的导电层; 设置在所述导电层上并且包括彼此分开堆叠的多个电极层的层叠体; 设置在所述导电层中的耦合部分; 整体设置在所述层叠体和所述连结部的半导体部; 设置在所述半导体部分和所述多个电极层之间的电荷存储膜; 以及互连部，其一体地设置在所述层叠体和所述导电层中，并且在所述层叠体的层叠方向上延伸。 互连部分包括设置在导电层中的侧表面，并且侧表面与耦合部分中的半导体部分的整个侧表面接触。

公开(公告)号：US20160071868A1

公开(公告)日：2016-03-10

申请号：US14597580

申请日：2015-01-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya ARAI

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/792

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Abstract translation: 根据一个实施例，半导体存储器件包括衬底; 设置在基板上的绝缘层; 设置在所述绝缘层上的导电层; 设置在所述导电层上并且分别设置在所述多个电极层中的多个电极层和多个绝缘层的层叠体; 穿过所述层叠体的柱状部分到达所述导电层并且在层叠体堆叠的第一方向上延伸; 和源层。 柱状部分包括设置在通道体和各个电极层之间的通道体和电荷存储膜。 导电层包括具有导电性并与沟道本体的下端部分接触的第一膜; 以及设置成被第一膜覆盖的气隙。

公开(公告)号：US20170154852A1

公开(公告)日：2017-06-01

申请号：US15057406

申请日：2016-03-01

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kenichi YASUDA ,  Shinya ARAI

IPC: H01L23/544 ,  H01L21/768 ,  H01L21/027 ,  H01L21/28 ,  H01L21/66 ,  H01L21/033 ,  H01L27/115

CPC classification number: H01L23/544 ,  G03F1/42 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76877 ,  H01L22/20 ,  H01L27/11582 ,  H01L28/00 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.

公开(公告)号：US20170062459A1

公开(公告)日：2017-03-02

申请号：US15001991

申请日：2016-01-20

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yasuhito YOSHIMIZU ,  Akifumi GAWASE ,  Kei WATANABE ,  Shinya ARAI

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/06 ,  H01L21/768 ,  H01L21/764 ,  H01L23/535 ,  H01L29/423 ,  H01L21/306

CPC classification number: H01L27/11582 ,  H01L21/764 ,  H01L23/53295

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.

Abstract translation: 根据一个实施例，半导体器件包括衬底，层叠体，第二气隙，第一绝缘膜，半导体膜和堆叠膜。 层叠体设置在基板上方，并且包括经由第一气隙堆叠的多个电极膜。 第二气隙在层叠体的堆叠方向上延伸。 第二气隙沿与层叠方向交叉的第一方向分离。 第一绝缘膜设置在层叠体的上方并覆盖第二气隙的上端。 叠层膜设置在电极膜的侧表面和与电极膜的侧表面相对的半导体膜的侧表面之间。 层叠膜与电极膜的侧面和半导体膜的侧面接触。

公开(公告)号：US20140021555A1

公开(公告)日：2014-01-23

申请号：US13780140

申请日：2013-02-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shota ISHIBASHI ,  Shinya ARAI ,  Gaku SUDO

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor device according to an embodiment includes forming element isolation regions and active areas on a surface of a semiconductor substrate. A plurality of gate electrodes are formed above the active areas. Recesses that recess below surfaces of the element isolation regions are formed in the active areas by selectively etching the active areas between the gate electrodes. An interlayer dielectric film is deposited on the active areas, the element isolation regions, and the gate electrodes. A contact holes are formed on the recesses by etching the interlayer dielectric film using anisotropic etching. A bottom of each contact holes is widened by further etching the interlayer dielectric film on an inner wall of each contact hole using isotropic etching. Contacts contacting the recesses in the active areas are formed by embedding a conductive material in the contact holes.

Abstract translation: 根据实施例的半导体器件的制造方法包括在半导体衬底的表面上形成元件隔离区域和有源区域。 多个栅电极形成在有源区上方。 通过选择性蚀刻栅电极之间的有源区，在有源区中形成凹陷在元件隔离区的表面下方的凹陷。 在有源区域，元件隔离区域和栅极电极上沉积层间绝缘膜。 通过使用各向异性蚀刻蚀刻层间绝缘膜，在凹部上形成接触孔。 通过使用各向同性蚀刻进一步蚀刻每个接触孔的内壁上的层间电介质膜来扩大每个接触孔的底部。 通过在导电孔中嵌入导电材料来形成与活性区域中的凹部接触的接触。

公开(公告)号：US20170263636A1

公开(公告)日：2017-09-14

申请号：US15266850

申请日：2016-09-15

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takashi ISHIDA ,  Jun FUJIKI ,  Shinya ARAI ,  Fumitaka ARAI ,  Hideaki AOCHI ,  Kotaro FUJII

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.

公开(公告)号：US20170077140A1

公开(公告)日：2017-03-16

申请号：US15344021

申请日：2016-11-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya ARAI

IPC: H01L27/115 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/792

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Abstract translation: 根据一个实施例，半导体存储器件包括衬底; 设置在基板上的绝缘层; 设置在所述绝缘层上的导电层; 设置在所述导电层上并且分别设置在所述多个电极层中的多个电极层和多个绝缘层的层叠体; 穿过所述层叠体的柱状部分到达所述导电层并且在层叠体堆叠的第一方向上延伸; 和源层。 柱状部分包括设置在通道体和各个电极层之间的通道体和电荷存储膜。 导电层包括具有导电性并与沟道本体的下端部分接触的第一膜; 以及设置成被第一膜覆盖的气隙。

公开(公告)号：US20170053935A1

公开(公告)日：2017-02-23

申请号：US15345790

申请日：2016-11-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract translation: 一种半导体存储器件，包括：包括半导体材料，第一电极膜，第一绝缘膜，堆叠体和三个或更多个半导体柱的连接构件。 层叠体包括交替堆叠的第二电极膜和第二绝缘膜。 半导体柱沿着两个或更多个方向排列，沿层叠方向延伸，穿过层叠体和第一绝缘膜，并连接到连接构件。 该装置包括设置在半导体柱和层叠体之间以及连接构件和第一电极膜之间的第三绝缘膜。 至少在一个第二电极膜和第三绝缘膜之间设置电荷存储层。