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公开(公告)号：US12300343B2
公开(公告)日：2025-05-13
申请号：US18053896
申请日：2022-11-09
Applicant: Kioxia Corporation
Inventor： Marie Takada , Masanobu Shirakawa , Hideki Yamada , Ryo Yamaki
IPC: G11C16/06 , G11C11/4074 , G11C11/4096 , G11C29/52
Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.
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公开(公告)号：US11940871B2
公开(公告)日：2024-03-26
申请号：US17895465
申请日：2022-08-25
Applicant: KIOXIA CORPORATION
Inventor： Yuki Mandai , Shuou Nomura , Ryo Yamaki , Toshikatsu Hida
CPC classification number: G06F11/1024 , G11C16/08 , G11C16/26
Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.
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公开(公告)号：US12094541B2
公开(公告)日：2024-09-17
申请号：US17452463
申请日：2021-10-27
Applicant: Kioxia Corporation
Inventor： Tsukasa Tokutomi , Masanobu Shirakawa , Kengo Kurose , Marie Takada , Ryo Yamaki , Kiyotaka Iwasaki , Yoshihisa Kojima
IPC: G11C7/00 , G06F3/06 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/26 , G11C29/52 , G11C16/08 , H10B43/27 , H10B43/35
CPC classification number: G11C16/26 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C11/5671 , G11C16/0483 , G11C29/52 , G11C16/08 , H10B43/27 , H10B43/35
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.
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公开(公告)号：US11443829B2
公开(公告)日：2022-09-13
申请号：US17010041
申请日：2020-09-02
Applicant: Kioxia Corporation
Inventor： Ryo Yamaki , Yuki Komatsu
Abstract: A memory system includes a non-volatile memory and a controller configured to divides an n-dimensional space into a plurality of regions by a plurality of hyperplanes, assign a representative point of a read level for reading data from a plurality of memory cells to each region, trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, and cause the memory to read data of the cells by applying a voltage of the second read level.
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公开(公告)号：US20250054564A1
公开(公告)日：2025-02-13
申请号：US18795818
申请日：2024-08-06
Applicant: Kioxia Corporation
Inventor： Marie Takada , Masanobu Shirakawa , Naomi Takeda , Ryo Yamaki , Shogo Muto , Hideki Yamada
Abstract: According to one embodiment, a memory system includes a memory chip and a memory controller. A first cell unit and a second cell unit are classified into a first group. A third cell unit is classified into a second group. The memory controller is configured to use a first correction amount of a read voltage when data of the first group is read and to use a second correction amount of the read voltage when data of the second group is read. When a time difference from a write operation of the first cell unit to the write operation of the second cell unit exceeds a reference value, the memory controller is configured to change a boundary position between the first group and the second group to between the first cell unit and the second cell unit, and to classify the second cell unit into the second group.
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Patent Agency Ranking
公开(公告)号：US12165725B2
公开(公告)日：2024-12-10
申请号：US18230151
申请日：2023-08-03
Applicant: Kioxia Corporation
Inventor： Ryo Yamaki , Masanobu Shirakawa , Naomi Takeda , Takashi Nakagawa , Shingo Yanagawa
Abstract: According to one embodiment, a memory system includes a non-volatile first memory with first storage areas. A controller executes a first read operation on a second storage area of the first storage areas. When an error correction in the first read operation fails, the controller acquires a first measured value being a value of a read voltage for suppressing the number of occurrences of error bits in the second storage area. The controller updates, on the basis of the first measured value, one of first candidate values of the read voltage with a second candidate value. When the error correction in a second read operation for a third storage area of the first storage areas fails, the controller executes the read operation once or more on the third storage area by using, as the read voltages, different first candidate values of the first candidate values.
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公开(公告)号：US11347584B2
公开(公告)日：2022-05-31
申请号：US16807220
申请日：2020-03-03
Applicant: Kioxia Corporation
Inventor： Masanobu Shirakawa , Hideki Yamada , Marie Takada , Ryo Yamaki , Osamu Torii , Naomi Takeda
Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.
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公开(公告)号：US11093173B2
公开(公告)日：2021-08-17
申请号：US16790807
申请日：2020-02-14
Applicant: Kioxia Corporation
Inventor： Ryo Yamaki , Gibeom Park , Youyang Ng , Koji Horisaki , Kazuhisa Horiuchi
Abstract: According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.
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公开(公告)号：US10957400B1
公开(公告)日：2021-03-23
申请号：US16802477
申请日：2020-02-26
Applicant: KIOXIA CORPORATION
Inventor： Koji Horisaki , Kazuhisa Horiuchi , Ryo Yamaki , Gibeom Park , Youyang Ng
Abstract: A memory controller performs a reference read on a plurality of memory cells using reference read voltages, generates a histogram indicating the number of memory cells in different threshold voltage bins based on results of the reference read, estimates actual read voltages based on the histogram and a first estimation function, and reads data using the actual read voltages. When reading of the data with the actual read voltages estimated using the first estimation function fails, the memory controller estimates actual read voltages using a second estimation function different from the first estimation function and reads the data with the actual read voltages estimated using the second estimation function.
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公开(公告)号：US11424002B2
公开(公告)日：2022-08-23
申请号：US17158161
申请日：2021-01-26
Applicant: Kioxia Corporation
Inventor： Naomi Takeda , Ryo Yamaki , Masanobu Shirakawa
Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.
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