公开(公告)号：US4895767A

公开(公告)日：1990-01-23

申请号：US208845

申请日：1988-06-17

申请人： Kaoru Mori ,  Naoki Shimoyama ,  Takashi Taniquchi

发明人： Kaoru Mori ,  Naoki Shimoyama ,  Takashi Taniquchi

IPC分类号： C09D163/00 ,  C09D183/04 ,  G02B1/10

CPC分类号： G02B1/105 ,  C09D163/00 ,  C09D183/04 ,  Y10T428/256 ,  Y10T428/31507 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31518 ,  Y10T428/31612 ,  Y10T428/31663

摘要： A transparent article comprising on the surface of a transparent substrate a cured transparent coating film composed of a composition comprising 100 parts by weight of an organic silicon compound represented by the following general formula (I) and/or a hydrolysis product thereof:R.sup.1.sub.a R.sup.2.sub.b Si(OR.sup.3).sub.4-a-b (I)wherein R.sup.1 and R.sup.2 each stand for an alkyl group, an alkenyl group, an aryl group or a hydrocarbon group having a halogen group, an epoxy group, a glycidoxy group, an amino group, a mercapto group, a methacryloxy group or a cyano group, R.sup.3 stands for an alkyl group having 1 to 8 carbon atoms, an alkoxyalkyl group, an acyl group or a phenyl group, and a and b are 0 or 1,10 to 300 parts by weight of a polyfunctional epoxy resin having an aromatic ring and/or an aliphatic ring and 25 to 800 parts by weight of antimony oxide fine particles having an average particle size of 1 to 200 m.mu..

摘要翻译： 一种透明制品，在透明基材的表面上包含固化的透明涂膜，所述固化的透明涂膜由包含100重量份由下列通式（I）表示的有机硅化合物和/或其水解产物的组合物组成：R1aR2bSi（OR3） ）4-ab（I）其中R 1和R 2各自代表烷基，烯基，芳基或具有卤素基团，环氧基，缩水甘油氧基，氨基，巯基， 甲基丙烯酰氧基或氰基，R3表示碳原子数1〜8的烷基，烷氧基烷基，酰基或苯基，a和b分别为0或1〜10〜300重量份 具有芳香环和/或脂肪族环的多官能环氧树脂和25〜800重量份平均粒径为1〜200μm的氧化锑微粒。

公开(公告)号：US08433960B2

公开(公告)日：2013-04-30

申请号：US13279111

申请日：2011-10-21

申请人： Kaoru Mori

发明人： Kaoru Mori

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C2029/1804

摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR (configuration register) control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads.

摘要翻译： 一种在测试时间内在多个CR中设定任意操作模式信息的半导体存储器。 当CR（配置寄存器）控制电路检测到写入命令以写入地址或读取命令以按预定顺序从地址读取时，CR控制电路在时分上更新多个CR中的每一个的操作模式信息 基础。 命令生成部分响应于来自外部的控制信号生成写命令，读命令或测试开始命令。 数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据 数据垫。

公开(公告)号：US08368175B2

公开(公告)日：2013-02-05

申请号：US12933946

申请日：2009-03-27

申请人： Takashi Nakagawa ,  Kaoru Mori ,  Nobuyuki Ikarashi ,  Makiko Oshida

发明人： Takashi Nakagawa ,  Kaoru Mori ,  Nobuyuki Ikarashi ,  Makiko Oshida

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L21/3142 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/316 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/40

摘要： Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1−x): x (0.01≦x≦0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

摘要翻译： 提供一种电容器，其实现具有大的相对介电常数的电容绝缘膜，并且即使占用空间小，漏电流减少，也具有足够的电容。 电容器包括：电容绝缘膜; 以及各自形成在电容绝缘膜的两侧的上电极和下电极。 电容绝缘膜是主要成分为Zr，Al和O的复合氧化物，Zr与Al的组成比设定为（1-x）：x（0.01＆nlE; x＆nlE; 0.15），由介电材料 具有晶体结构。 下电极由与至少电介质膜相邻的表面具有非晶结构的导体构成。

公开(公告)号：US20110038094A1

公开(公告)日：2011-02-17

申请号：US12937916

申请日：2009-04-16

申请人： Kaoru Mori ,  Takashi Nakagawa

发明人： Kaoru Mori ,  Takashi Nakagawa

IPC分类号： H01G4/008 ,  H01G4/00

CPC分类号： H01G4/008 ,  H01G4/12 ,  H01G4/33

摘要： A capacitor includes a plurality of laminated thin layers, has a structure in which a lower electrode layer, a dielectric layer and an upper electrode layer are laminated in sequence, a main material of the lower electrode layer is TiN or ZrN, the lower electrode layer contains oxygen, and concentration of the oxygen contained in the lower electrode layer is less than 21 at %.

摘要翻译： 电容器包括多个层叠薄层，具有下电极层，电介质层和上电极层依次层叠的结构，下电极层的主要材料为TiN或ZrN，下电极层 含有氧，下部电极层中所含的氧的浓度小于21原子％。

公开(公告)号：US07362630B2

公开(公告)日：2008-04-22

申请号：US11714766

申请日：2007-03-07

申请人： Kaoru Mori ,  Yoshiaki Okuyama

发明人： Kaoru Mori ,  Yoshiaki Okuyama

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/838

摘要： In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

摘要翻译： 为了给予所有存储块相同的结构，在每个存储块中形成冗余字线和冗余位线。 冗余列选择线公共地连接到存储器块。 列冗余电路形成为对应于各自的存储器组，每个存储器组由规定数量的存储块组成，并且根据使能信号变为有效。 当所有行命中信号被去激活时，列冗余选择电路根据块地址信号激活使能信号。 当行命中信号之一被激活时，列冗余选择电路激活对应于激活的行命中信号的使能信号。 由于可以根据行命中信号使任意存储器组的列冗余电路有效，可以在不使访问操作期间的电特性恶化的情况下增加故障排除效率。

公开(公告)号：US07280029B2

公开(公告)日：2007-10-09

申请号：US10423014

申请日：2003-04-25

申请人： Kaoru Mori ,  Atsushi Kamijo

发明人： Kaoru Mori ,  Atsushi Kamijo

IPC分类号： H01L43/00

CPC分类号： H01L43/08 ,  Y10T428/32

摘要： A laminated ferrimagnetic thin film consists of two ferromagnetic layers and a non-magnetic intermediate layer sandwiched therebetween. The respective ferromagnetic layers are magnetically coupled in an anti-ferromagnetic manner through the non-magnetic intermediate layer. Each ferromagnetic layer consists of a plurality of layers. In each ferromagnetic layer, a layer which is in contact with the non-magnetic intermediate layer is formed of Co or an alloy including Co while at least one layer is formed of Ni or an alloy including Ni, and its film thickness is determined to be at least 60% or more of a film thickness of each ferromagnetic layer.

摘要翻译： 叠层铁磁薄膜由两个铁磁层和夹在其间的非磁性中间层组成。 相应的铁磁层通过非磁性中间层以反铁磁方式磁耦合。 每个铁磁层由多个层组成。 在每个铁磁层中，与非磁性中间层接触的层由Co或包含Co的合金形成，而至少一层由Ni或包含Ni的合金形成，并且其膜厚被确定为 每个铁磁层的膜厚度的至少60％以上。

公开(公告)号：US07271698B2

公开(公告)日：2007-09-18

申请号：US10896082

申请日：2004-07-22

申请人： Kaoru Mori ,  Atsushi Kamijo

发明人： Kaoru Mori ,  Atsushi Kamijo

IPC分类号： H01L43/00

CPC分类号： H01L43/08 ,  Y10T428/32

摘要： A laminated ferrimagnetic thin film consists of two ferromagnetic layers and a non-magnetic intermediate layer sandwiched therebetween. The respective ferromagnetic layers are magnetically coupled in an antiferromagnetic manner through the non-magnetic intermediate layer. Each ferromagnetic layer consists of a plurality of layers. In each ferromagnetic layer, a layer which is in contact with the non-magnetic intermediate layer is formed of Co or an alloy including Co while at least one layer is formed of Ni or an alloy including Ni, and its film thickness is determined to be at least 60% or more of a film thickness of each ferromagnetic layer.

摘要翻译： 叠层铁磁薄膜由两个铁磁层和夹在其间的非磁性中间层组成。 相应的铁磁层通过非磁性中间层以反铁磁方式磁耦合。 每个铁磁层由多个层组成。 在每个铁磁层中，与非磁性中间层接触的层由Co或包含Co的合金形成，而至少一层由Ni或包含Ni的合金形成，并且其膜厚被确定为 每个铁磁层的膜厚度的至少60％以上。

公开(公告)号：US07242047B2

公开(公告)日：2007-07-10

申请号：US11208370

申请日：2005-08-19

申请人： Kaoru Mori ,  Tetsuhiro Suzuki ,  Yoshiyuki Fukumoto ,  Sadahiko Miura

发明人： Kaoru Mori ,  Tetsuhiro Suzuki ,  Yoshiyuki Fukumoto ,  Sadahiko Miura

IPC分类号： H01L29/76

CPC分类号： G11C11/16 ,  B82Y25/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01L43/08

摘要： A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit writing data into the free magnetic layer through developing a first write current on the first interconnection, and then developing a second write current on the second interconnection with the first write current turned on. The free magnetic layer includes: first to N-th ferromagnetic layers and first to (N−1)-th non-magnetic layers with N being equal to or more than 4, the i-th non-magnetic layer being disposed between the i-th and (i+1)-th ferromagnetic layers with i being any of natural numbers equal to or less than N−1. The free magnetic layer is designed so that antiferromagnetic coupling(s) between the j-th and (j+1)-th ferromagnetic layers is stronger than that between the first and second ferromagnetic layers, j being any of integers ranging from 2 to N−2.

摘要翻译： 磁存储器包括：包括自由磁性层的磁阻元件; 第一互连件，其在第一方向上倾斜于所述自由磁性层的容易轴线延伸; 沿与第一方向大致正交的第二方向延伸的第二互连; 以及写入电路，通过在所述第一互连上形成第一写入电流将数据写入所述自由磁性层，然后在所述第二互连上开启第二写入电流，所述第一写入电流导通。 自由磁性层包括：第一至第N铁磁层和N等于或大于4的第一至第（N-1）个非磁性层，第i个非磁性层设置在i 和第（i + 1）个铁磁层，其中i为等于或小于N-1的任意自然数。 自由磁性层被设计成使得第j和第（j + 1）个铁磁层之间的反铁磁耦合比第一和第二铁磁层之间的反铁磁耦合更强，j是从2到N的整数中的任何一个 -2。

公开(公告)号：US07145825B2

公开(公告)日：2006-12-05

申请号：US10800831

申请日：2004-03-16

申请人： Kaoru Mori ,  Katuhiro Mori ,  Shinichi Yamada ,  Kuninori Kawabata ,  Shigemasa Ito

发明人： Kaoru Mori ,  Katuhiro Mori ,  Shinichi Yamada ,  Kuninori Kawabata ,  Shigemasa Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

摘要翻译： 一种在移位寄存器的驱动控制信号中具有低功耗的半导体存储器件。 该装置包含多个存储单元阵列，每个存储单元阵列由预定数量的存储单元行组成。 一组移位寄存器耦合到每个单元阵列，并且第n组移位寄存器根据给定的控制信号依次激活字线选择信号，使得第n个单元阵列的相应字线将被刷新。 还耦合到每个单元阵列是移位寄存器控制器。 当第n个单元阵列被刷新时，第n个移位寄存器控制器向第n组移位寄存器提供控制信号。 当完成该单元阵列的刷新时，第n移位寄存器控制器将控制信号转发到第（n + 1）个移位寄存器组，从而启动第（n + 1）个单元阵列的刷新操作。

公开(公告)号：US20060098523A1

公开(公告)日：2006-05-11

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。